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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. publication# 21336 rev: a amendment/ 0 issue date: may 1997 d ra f t am186 tm ed/edlv high performance, 80c186- and 80c188-compatible, 16-bit embedded microcontrollers distinctive characteristics n e86 tm family 80c186- and 80c188-compatible microcontroller with enhanced bus interface C lower system cost with higher performance C 3.3-v 0.3-v operation (am186edlv microcontrollers) n programmable dram controller C supports zero-wait-state operation with 50-ns dram at 40 mhz, 60-ns @ 33 mhz, 70-ns @ 25 mhz C includes programmable cas -before-ras refresh capability n high performance C 20-, 25-, 33-, and 40-mhz operating frequencies C zero-wait-state operation at 40 mhz with 70-ns static memory C 1-mbyte memory address space C 64-kbyte i/o space n enhanced features provide improved memory access and remove the requirement for a 2x clock input C nonmultiplexed address bus C processor operates at the clock input frequency C 8-bit or 16-bit programmable bus sizing including 8-bit boot option n enhanced integrated peripherals C 32 programmable i/o (pio) pins C two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers C serial port hardware handshaking with cts , rts , enrx , and rtr selectable for each port C improved serial port operation enhances 9-bit dma support C independent serial port baud rate generators C dma to and from the serial ports C watchdog timer can generate nmi or reset C a pulse-width demodulation option C a data strobe, true asynchronous bus interface option included for den C reset configuration register n familiar 80c186 peripherals C two independent dma channels C programmable interrupt controller with up to 8 ex- ternal and 8 internal interrupts C three programmable 16-bit timers C programmable memory and peripheral chip-select logic C programmable wait state generator C power-save clock divider n software-compatible with the 80c186 and 80c188 microcontrollers with widely available native development tools, applications, and system software n a compatible evolution of the am186em, am186es, and am186er microcontrollers n available in the following packages: C 100-pin, thin quad flat pack (tqfp) C 100-pin, plastic quad flat pack (pqfp) general description the am186 tm ed/edlv microcontrollers are part of the amd e86 tm family of embedded microcontrollers and mi- croprocessors based on the x86 architecture. the am186ed/edlv microcontrollers are the ideal upgrade for 80c186/188 designs requiring 80c186/188 compat- ibility, increased performance, serial communications, a direct bus interface, and more than 64k of memory. the am186ed/edlv microcontrollers integrate a com- plete dram controller to take advantage of low dram costs. this reduces memory subsystem costs while maintaining sram performance.the am186ed/edlv microcontrollers also integrate the functions of a cpu, nonmultiplexed address bus, three timers, watchdog timer, chip selects, interrupt controller, two dma control- lers, two asynchronous serial ports, programmable bus sizing, and programmable i/o (pio) pins on one chip. compared to the 80c186/188 microcontrollers, the am186ed/edlv microcontrollers enable designers to reduce the size, power consumption, and cost of em- bedded systems, while increasing reliability, functional- ity, and performance. the am186ed/edlv microcontrollers have been designed to meet the most common requirements of embedded products developed for the communications, office automation, mass storage, and general embedded markets. specific applications include pbxs, multiplexers, modems, disk drives, hand-held and desktop terminals, fax machines, printers, photocopiers, and industrial controls.
2 am186ed/edlv microcontrollers preliminary d ra f t am186ed/edlv microcontrollers block diagram notes: *all pio signals are shared with other physical pins. see the pin descriptions beginning on page 21 and table 2 on page 29 for information on shared functions. ** rts 1/rtr 1 and cts 1/enrx 1 are multiplexed with pcs 3 and pcs 2, respectively. see the pin descriptions beginning on page 21. s 1Cs 0 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int6Cint4** int3/inta 1/irq int2/inta 0/pwd** int1/select int0 tmrout0 tmrout1 drq0/int5** drq1/int6** v cc gnd tmrin0 tmrin1 ardy srdy dt/r den /ds hold hlda asynchronous serial port 0 txd0 rxd0 nmi a19Ca0 ad15Cad0 ale bhe /aden wr wlb whb rd res lcs /once 0/ras 0 mcs 2/lcas pcs 6/a2 pcs 3Cpcs 0** pcs 5/a1 ucs /once 1 x2 x1 mcs 3/ras 1 pio unit pio31C pio0* control registers s6/clkdiv 2 uzi txd1 rxd1 cts 0/enrx 0 cts 1/enrx 1** rts 0/rtr 0 rts 1/rtr 1** watchdog timer (wdt) pulse width demod- ulator (pwd) pwd** asynchronous serial port 1 mcs 1/ucas s 2/btsel dram control unit mcs 0
am186ed/edlv microcontrollers 3 preliminary d ra f t ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. C20 = 20 mhz C25 = 25 mhz C33 = 33 mhz C40 = 40 mhz temperature range c= ed commercial (t c =0 c to +100 c) c = edlv commercial (t c =0 c to +70 c) i = ed industrial (t a =C40 c to +85 c) where: t c = case temperature where: t a = ambient temperature speed option device number/description lead forming \w=trimmed and formed valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: the industrial version of the am186ed as well as the am186edlv are available in 20 and 25 mhz operating frequencies only. the am186ed and am186edlv microcontrollers are all functionally the same except for their dc characteristics and available frequencies. note: there is no 188 version of the am186ed/ edlv. the same 8-bit external bus capabilities can be achieved using the 8-bit boot capability and programmable bus sizing options. valid combinations package type v=100-pin thin quad flat pack (tqfp) k=100-pin plastic quad flat pack (pqfp) am186ed = high-performance, 80c186-compatible, 16-bit embedded microcontroller am186edlv = high-performance, 80l186-compatible , low-voltage, 16-bit embedded microcontroller am186edlvC25 valid combinations am186edlvC20 vc\w or kc\w am186edC25 am186edC33 am186edC40 am186edC20 ki\w 1 am186edC25 am186edC20 vc\w or kc\w note: the industrial version of the am186ed is offered only in the pqfp package. -40 k c \w am186 tm ed/edlv
4 am186ed/edlv microcontrollers preliminary d ra f t table of contents distinctive characteristics ........................................................................................... 1 general description .......................................................................................................... 1 am186ed/edlv microcontrollers block diagram ................................................... 2 ordering information ....................................................................................................... 3 standard products ........................................................................................................... 3 related amd products ...................................................................................................... 9 e86 ? family devices ...................................................................................................... 9 related documents ....................................................................................................... 10 third-party development support products .................................................................. 10 customer service .......................................................................................................... 10 key features and benefits ............................................................................................ 10 application considerations .............................................................................................11 comparing the am186ed/edlv to the am186es/eslv microcontrollers ........ 12 integrated dram controller ........................................................................................... 12 enhanced refresh control unit ..................................................................................... 13 option to overlap dram with pcs ............................................................................... 13 additional serial port mode for dma support of 9-bit protocols .................................... 13 option to boot from 8- or 16-bit memory ....................................................................... 13 improved external bus master support ......................................................................... 13 psram controller removed ......................................................................................... 13 tqfp connection diagrams and pinouts .................................................................. 14 top side view100-pin thin quad flat pack (tqfp) ................................................. 14 tqfp pin designations ....................................................................................................... 15 sorted by pin number .................................................................................................... 15 sorted by pin name ....................................................................................................... 16 pqfp connection diagrams and pinouts .................................................................. 17 top side view100-pin plastic quad flat pack (pqfp) ............................................. 17 pqfp pin designations....................................................................................................... 18 sorted by pin number .................................................................................................... 18 sorted by pin name ....................................................................................................... 19 logic symbolam186ed/edlv microcontrollers ................................................. 20 pin descriptions ................................................................................................................. 21 pins that are used by emulators .................................................................................. 21 pin terminology ............................................................................................................. 21 a19Ca0 (a19/pio9, a18/pio8, a17/pio7) .................................................................... 21 ad15Cad8 ..................................................................................................................... 21 ad7Cad0 ....................................................................................................................... 21 ale ................................................................................................................................ 21 ardy ............................................................................................................................. 22 bhe /aden ..................................................................................................................... 22 clkouta ...................................................................................................................... 22 clkoutb ...................................................................................................................... 22 cts 0/enrx 0/pio21 ...................................................................................................... 22 den /ds /pio5 ................................................................................................................ 23 drq0/int5/pio12 ......................................................................................................... 23 drq1/int6/pio13 ......................................................................................................... 23 dt/r /pio4 ..................................................................................................................... 23 gnd ............................................................................................................................... 23 hlda ............................................................................................................................. 23 hold ............................................................................................................................. 23 int0 ............................................................................................................................... 24 int1/select ................................................................................................................ 24
am186ed/edlv microcontrollers 5 preliminary d ra f t int2/inta 0/pwd/pio31 ................................................................................................ 24 int3/inta 1/irq ............................................................................................................. 24 int4/pio30 .................................................................................................................... 25 lcs /once 0/ras 0 ........................................................................................................ 25 mcs 0/pio14 .................................................................................................................. 25 mcs 1/ucas /pio15 ....................................................................................................... 25 mcs2 /lcas /pio24 ....................................................................................................... 25 mcs3 /ras 1/pio25 ....................................................................................................... 26 nmi ................................................................................................................................ 26 pcs 1/pio17, pcs 0/pio16 ............................................................................................ 26 pcs 2/cts 1/enrx 1/pio18 ........................................................................................... 27 pcs 3/rts 1/rtr 1/pio19 .............................................................................................. 27 pcs 5/a1/pio3 ............................................................................................................... 27 pcs 6/a2/pio2 ............................................................................................................... 28 pio31Cpio0 (shared) .................................................................................................... 28 rd .................................................................................................................................. 28 res ................................................................................................................................ 28 rts 0/rtr 0/pio20 ........................................................................................................ 30 rxd0/pio23 .................................................................................................................. 30 rxd1/pio28 .................................................................................................................. 30 s 2/btsel ...................................................................................................................... 30 s 1Cs 0 ............................................................................................................................ 30 s6/clkdiv 2/pio29 ....................................................................................................... 30 srdy/pio6 .................................................................................................................... 30 tmrin0/pio11 ............................................................................................................... 31 tmrin1/pio0 ................................................................................................................ 31 tmrout0/pio10 .......................................................................................................... 31 tmrout1/pio1 ............................................................................................................ 31 txd0/pio22 ................................................................................................................... 31 txd1/pio27 ................................................................................................................... 31 ucs /once 1 .................................................................................................................. 31 uzi /pio26 ...................................................................................................................... 31 v cc ................................................................................................................................ 31 whb ............................................................................................................................... 31 wlb ............................................................................................................................... 32 wr ................................................................................................................................. 32 x1 ................................................................................................................................... 32 x2 ................................................................................................................................... 32 functional description .................................................................................................. 33 memory organization ..................................................................................................... 33 i/o space ....................................................................................................................... 33 bus operation ..................................................................................................................... 34 bus interface unit ............................................................................................................. 36 nonmultiplexed address bus ......................................................................................... 36 dram address multiplexing .......................................................................................... 36 programmable bus sizing ............................................................................................. 37 byte-write enables ........................................................................................................ 37 data strobe bus interface option .................................................................................. 37 dram interface ................................................................................................................... 37 peripheral control block ............................................................................................ 38 reading and writing the pcb ........................................................................................ 38
6 am186ed/edlv microcontrollers preliminary d ra f t clock and power management .................................................................................... 40 phase-locked loop ....................................................................................................... 40 crystal-driven clock source .......................................................................................... 40 external source clock ................................................................................................... 41 system clocks ............................................................................................................... 41 power-save operation ................................................................................................... 41 initialization and processor reset .................................................................................. 41 reset configuration register ......................................................................................... 41 chip-select unit .................................................................................................................. 42 chip-select timing ......................................................................................................... 42 ready and wait-state programming ............................................................................. 42 chip-select overlap ....................................................................................................... 42 upper memory chip select ............................................................................................ 43 low memory chip select ............................................................................................... 43 midrange memory chip selects ..................................................................................... 43 peripheral chip selects ................................................................................................. 43 refresh control unit ...................................................................................................... 44 interrupt control unit .................................................................................................. 44 timer control unit ............................................................................................................ 45 watchdog timer ............................................................................................................. 45 pulse width demodulation ............................................................................................ 45 direct memory access .................................................................................................... 46 dma operation .............................................................................................................. 46 dma channel control registers .................................................................................... 47 dma priority ................................................................................................................... 47 asynchronous serial ports ......................................................................................... 47 dma transfers through the serial port .......................................................................... 48 programmable i/o (pio) pins ........................................................................................... 48 absolute maximum ratings ............................................................................................ 49 operating ranges ............................................................................................................. 49 dc characteristics over commercial and industrial operating ranges . 49 capacitance ......................................................................................................................... 50 power supply current ................................................................................................... 50 thermal characteristics ............................................................................................... 51 tqfp package .............................................................................................................. 51 typical ambient temperatures ....................................................................................... 52 commercial and industrial switching characteristics and waveforms .. 57 key to switching waveforms ......................................................................................... 57 alphabetical key to switching parameter symbols ....................................................... 58 numerical key to switching parameter symbols ........................................................... 61 switching characteristics over commercial and industrial operating ranges ............................................................................................... 64 read cycle (20 mhz and 25 mhz) ................................................................................ 64 switching characteristics over commercial operating ranges ................. 65 read cycle (33 mhz and 40 mhz) ................................................................................ 65 read cycle waveforms ................................................................................................... 66 switching characteristics over commercial and industrial operating ranges ............................................................................................... 67 write cycle (20 mhz and 25 mhz) ................................................................................ 67 switching characteristics over commercial operating ranges ................. 68 write cycle (33 mhz and 40 mhz) ................................................................................ 68 write cycle waveforms .................................................................................................. 69
am186ed/edlv microcontrollers 7 preliminary d ra f t switching characteristics over commercial and industrial operating ranges ............................................................................................... 70 dram ............................................................................................................................ 70 dram read cycle timing with no-wait states ............................................................ 71 dram read cycle timing with wait state(s) ................................................................ 71 dram write cycle timing with no-wait states ............................................................. 72 dram write cycle timing with wait state(s) ............................................................... 72 dram cas -before-ras cycle timing .......................................................................... 73 switching characteristics over commercial and industrial operating ranges ............................................................................................... 74 interrupt acknowledge cycle (20 mhz and 25 mhz) ..................................................... 74 switching characteristics over commercial operating ranges ................. 75 interrupt acknowledge cycle (33 mhz and 40 mhz) ..................................................... 75 interrupt acknowledge cycle waveforms ........................................................... 76 switching characteristics over commercial and industrial operating ranges ............................................................................................... 77 software halt cycle (20 mhz and 25 mhz) ................................................................... 77 switching characteristics over commercial operating ranges ................. 77 software halt cycle (33 mhz and 40 mhz) ................................................................... 77 software halt cycle waveforms ............................................................................... 78 switching characteristics over commercial and industrial operating ranges ............................................................................................... 79 clock (20 mhz and 25 mhz) .......................................................................................... 79 switching characteristics over commercial operating ranges ................. 80 clock (33 mhz and 40 mhz) .......................................................................................... 80 clock waveforms .............................................................................................................. 81 clock waveformsactive mode ................................................................................... 81 clock waveformspower-save mode .......................................................................... 81 switching characteristics over commercial and industrial operating ranges ............................................................................................... 82 ready and peripheral (20 mhz and 25 mhz) ................................................................ 82 switching characteristics over commercial operating ranges ................. 82 ready and peripheral (33 mhz and 40 mhz) ................................................................ 82 synchronous, asynchronous, and peripheral waveforms ............................ 83 synchronous ready waveforms ................................................................................... 83 asynchronous ready waveforms .................................................................................. 83 peripheral waveforms ................................................................................................... 83 switching characteristics over commercial and industrial operating ranges ............................................................................................... 84 reset and bus hold (20 mhz and 25 mhz) ................................................................... 84 switching characteristics over commercial operating ranges ................ 84 reset and bus hold (33 mhz and 40 mhz) ................................................................... 84 reset and bus hold waveforms ................................................................................... 85 reset waveforms .......................................................................................................... 85 signals related to reset waveforms ............................................................................ 85 bus hold waveformsentering .................................................................................... 86 bus hold waveformsleaving ..................................................................................... 86 tqfp physical dimensions ............................................................................................... 87 pqfp physical dimensions .............................................................................................. 88
8 am186ed/edlv microcontrollers preliminary d ra f t list of figures figure 1 am186ed microcontroller example system design .............................................. 11 figure 2 80c186 microcontroller example system design ................................................. 12 figure 3 two-component address ...................................................................................... 33 figure 4 16-bit modenormal read and write operation ................................................. 34 figure 5 16-bit moderead and write with address bus disable in effect ....................... 35 figure 6 8-bit modenormal read and write operation ................................................... 35 figure 7 8-bit moderead and write with address bus disable in effect ......................... 36 figure 8 am186ed/edlv microcontrollers oscillator configurations ................................. 40 figure 9 clock organization ................................................................................................ 41 figure 10 dma unit block diagram ....................................................................................... 47 figure 11 typical i cc versus frequency for am186edlv microcontroller ............................. 50 figure 12 typical i cc versus frequency for am186ed microcontroller ................................. 50 figure 13 thermal resistance( c/watt) ................................................................................ 51 figure 14 thermal characteristics equations ........................................................................ 51 figure 15 typical ambient temperatures for pqfp with a 2-layer board ............................ 53 figure 16 typical ambient temperatures for tqfp with a 2-layer board ............................ 54 figure 17 typical ambient temperatures for pqfp with a 4-layer to 6-layer board .......... 55 figure 18 typical ambient temperatures for tqfp with a 4-layer to 6-layer board ........... 56 list of tables table 1 data byte encoding ............................................................................................... 22 table 2 numeric pio pin designations .............................................................................. 29 table 3 alphabetic pio pin designations ........................................................................... 29 table 4 bus cycle encoding ............................................................................................... 30 table 5 segment register selection rules ........................................................................ 33 table 6 dram pin interface ............................................................................................... 37 table 7 programming the bus width of am186ed/edlv microcontrollers ........................ 37 table 8 peripheral control block register map .................................................................. 39 table 9 am186ed/edlv microcontrollers maximum dma transfer rates ....................... 46 table 10 typical power consumption calculation for the am186edlv microcontroller ...... 50 table 11 thermal characteristics ( c/watt) ......................................................................... 51 table 12 typical power consumption calculation ............................................................... 52 table 13 junction temperature calculation ......................................................................... 52 table 14 typical ambient temperatures (c) for pqfp with a 2-layer board .................... 53 table 15 typical ambient temperatures (c) for tqfp with a 2-layer board .................... 54 table 16 typical ambient temperatures (c) for pqfp with a 4-layer to 6-layer board ... 55 table 17 typical ambient temperatures (c) for tqfp with a 4-layer to 6-layer board ... 56
am186ed/edlv microcontrollers 9 preliminary d ra f t related amd products e86 ? family devices device description 80c186 16-bit microcontroller 80c188 16-bit microcontroller with 8-bit external data bus 80l186 low-voltage, 16-bit microcontroller 80l188 low-voltage, 16-bit microcontroller with 8-bit external data bus am186em high-performance, 80c186-compatible, 16-bit embedded microcontroller am188em high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186emlv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188emlv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186es high-performance, 80c186-compatible, 16-bit embedded microcontroller am188es high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186eslv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188eslv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186ed high-performance, 80c186- and 80c188-compatible, 16-bit embedded microcontroller with 8- or 16- bit external data bus am186edlv high-performance, 80c186- and 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186er high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller with 32 kbyte of internal ram am188er high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 kbyte of internal ram lan ? sc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at microcontroller lansc400 single-chip, low-power, pc/at-compatible microcontroller lansc410 single-chip, pc/at-compatible microcontroller am386?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am386?sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am486?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus at peripheral microcontrollers 186 peripheral microcontrollers lansc400 microcon t roller 80c186 and 80c188 microcontrollers microprocessors lansc300 microcon t roller am386sx/dx microprocessors am486dx microprocessor time the e86 family of embedded microprocessors and microcontrollers am186es and am188es microcontrollers am186em and am188em microcontrollers am186 and am188 future lansc310 microcon t roller 80l186 and 80l188 microcontrollers am186emlv & am188emlv microcontrollers am186eslv & am188eslv microcontrollers 32-bit future am186er and am188er microcontrollers future k86 ? lansc410 microcontroller am486 future am186ed microcontroller
10 am186ed/edlv microcontrollers preliminary d ra f t related documents the following documents provide additional information regarding the am186ed/edlv microcontrollers: n am186ed/edlv microcontrollers users manual , order # 21335 n am186 and am188 family instruction set manual , order # 21267 n fusione86 sm catalog , order # 19255 n e86 family support tools brief , order # 20071 n fusione86 development tools reference cd, order # 21058 third-party development support products the fusione86 sm program of partnerships for application solutions provides the customer with an array of products designed to meet critical time-to- market needs. products and solutions available from the amd fusione86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. customer service the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the worldwide staff of amd field application engineers and factory support staff to answer e86 family hardware and software development questions. hotline and world wide web support for answers to technical questions, amd provides a toll-free number for direct access to our corporate applications hotline. also available is the amd world wide web home page and ftp site, which provides the latest e86 family product information, including technical information and data on upcoming product releases. for technical support questions on all e86 prod- ucts, send e-mail to lpd.support@amd.com. corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline world wide web home page and ftp site to access the amd home page go to: http://www.amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or via your web browser, go to ftp://ftp.amd.com. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com. documentation and literature free e86 family information such as data books, users manuals, data sheets, application notes, the fusione86 partner solutions catalog, and other litera- ture is available with a simple phone call. internation- ally, contact your local amd sales office for complete e86 family literature. literature ordering (800) 222-9323 toll-free for u.s. and canada (512) 602-5651 direct dial worldwide (512) 602-7639 fax (800) 222-9323 amd facts-on-demand? fax information service, toll- free for u.s. and canada key features and benefits the am186ed/edlv microcontrollers extend the amd family of microcontrollers based on the industry-stan- dard x86 architecture. the am186ed/edlv microcon- trollers are a higher-performance, highly integrated version of the 80c186/188 microprocessors, offering an attractive migration path. in addition, the am186ed/ edlv microcontrollers offer application-specific fea- tures that can enhance the system functionality of the am186es/eslv and am188es/eslv microcontrol- lers. upgrading to the am186ed/edlv microcontrol- lers is an attractive solution for several reasons: n programmable dram controller enables sys- tem designers to take advantage of low-cost dram and fully utilize the performance and flexibility of the x86 architecture. the dram controller supports zero wait-state performance with 50-ns dram at 40 mhz, or, if required, can be programmed with wait states. the am186ed/edlv microcontrollers pro- vide a cas -before-ras refresh unit. n minimized total system cost new and en- hanced peripherals and on-chip system interface logic on the am186ed/edlv microcontrollers re- duce the cost of existing 80c186/188 designs. n x86 software compatibility 80c186/188-com- patible and upward-compatible with the other mem- bers of the amd e86 family.
am186ed/edlv microcontrollers 11 preliminary d ra f t n enhanced performance the am186ed/edlv microcontrollers increase the performance of 80c186/188 systems, and the nonmultiplexed ad- dress bus offers unbuffered access to memory. n enhanced functionality the enhanced on-chip peripherals of the am186ed/edlv microcontrollers include two asynchronous serial ports, 32 pios, a watchdog timer, additional interrupt pins, a pulse width demodulation option, dma directly to and from the serial ports, 8-bit and 16-bit programmable bus sizing, a 16-bit reset configuration register, and en- hanced chip-select functionality. application considerations the integration enhancements of the am186ed/edlv microcontrollers provide a high-performance, low-sys- tem-cost solution for 16-bit embedded microcontroller designs. the nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus main- tains the value of previously engineered, customer- specific peripherals and circuits within the upgraded design. figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high per- formance with reduced system cost. memory interface the am186ed/edlv microcontrollers integrate a ver- satile memory controller which supports direct memory accesses to dram, sram, flash, eprom, and rom. no external glue logic is required and all required con- trol signals are provided. the peripheral chip selects have been enhanced to allow them to overlap the dram. this allows a small 1.5k portion of the dram memory space to be used for peripherals without bus contention. the improved memory timing specifications of the am186ed/edlv microcontrollers allow for zero-wait- state operation at 40 mhz using 50-ns dram, 70-ns sram, or 70-ns flash memory. for 60-ns dram one wait state is required at 40 mhz and zero wait states at 33 mhz and below. for 70-ns dram two wait states are required at 40 mhz, one wait state at 33 mhz, and zero wait states at 25 mhz and below. this reduces overall system cost by enabling the use of commonly available memory speeds and taking advantage of drams lower cost per bit over sram. figure 1 also shows an implementation of an rs-232 console or modem communications port. the rs-232 to cmos voltage-level converter is required for the electrical interface with the external device. clock generation the integrated clock generation circuitry of the am186ed/edlv microcontrollers enables the use of a 1x crystal frequency. the am186ed design in figure 1 achieves 40-mhz cpu operation, while using a 40- mhz crystal. figure 1. am186ed microcontroller example system design direct memory interface example figure 1 illustrates the direct memory interface of the am186ed microcontroller. the processors a19Ca0 bus connects to the memory address inputs, the ad bus connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. the odd a1Ca17 address pins connect to the dram multiplexed address bus. the rd output connects to the dram output enable (oe ) pin for read operations. write operations use the wr output connected to the dram write enable (we ) pin. the ucas and lcas pins provide byte selection. 0-6
12 am186ed/edlv microcontrollers preliminary d ra f t comparing the am186es/eslv to the am186ed/edlv microcontrollers compared to the am186es/eslv microcontrollers, the am186ed/edlv microcontrollers have the following additional features: n integrated dram controller n enhanced refresh control unit n option to overlap dram with peripheral chip select (pcs) n additional serial port mode for dma support of 9-bit protocols n option to boot from 8- or 16-bit memory n improved external bus master support n psram controller removed figure 1 shows an example system using a 40-mhz am186ed microcontroller. figure 2 shows a comparable system implementation with an 80c186. because of its superior integration, the am186ed/ edlv system does not require the support devices that are required on the 80c186 example system. in addition, the am186ed/edlv microcontrollers provide significantly better performance with its 40-mhz clock rate. integrated dram controller the integrated dram controller directly interfaces dram to support no-wait state dram interface up to 40 mhz. wait states can be inserted to support slower dram. all signals required by the dram are generated on the am186ed/edlv microcontrollers and no external logic is required. the dram multiplexed address pins are connected to the odd address pins starting with a1 on the am186ed/edlv microcontrollers to ma0 on the dram. the correct row and column addresses are generated on these pins during a dram access. the ucas and lcas are used to select which byte of the dram is accessed during a read or write. the ras 0 controls the lower bank of dram which starts at 00000h in the address map and is bounded by the lower memory size selected in the lmcs register. ras 1 controls the upper bank of dram which ends at fffffh and is bounded by the upper memory size in the umcs register. when ras 1 is enabled, ucs is automatically disabled. neither, either, or both dram banks can be activated. figure 2. 80c186 microcontroller example system design 25
am186ed/edlv microcontrollers 13 preliminary d ra f t enhanced refresh control unit the refresh control unit (rcu) is enhanced with two additional bits in the refresh counter to allow for longer refresh periods. the address generated during a refresh has been fixed to fffffh. when either bank of dram is enabled and the rcu is enabled, a cas - before-ras refresh will be generated based on the time period coded into the refresh counter. option to overlap dram with pcs the peripheral chip selects (pcs 0Cpcs 6) can overlap dram blocks with different wait states without external or internal bus contention. the ras 0 or ras 1 will assert along with the appropriate pcs . the ucas and lcas will not assert, preventing the dram from writing erroneously or driving the data bus during a read. the pcs must have the same or higher number of wait states than the dram. the pcs bus width will be determined by the lsiz or usiz bus widths as programmed in the auxcon register. additional serial port mode for dma support of 9-bit protocols a mode 7 was added to the serial port which enhances the direct memory access (dma) support for 9-bit protocols. using mode 2, the serial port can be programmed to interrupt only if the 9th bit is set, ignoring all 9th bit cleared byte receptions. mode 3 receives all bytes, whether the 9th bit is set or cleared. mode 7 also receives all bytes whether the 9th bit is set or cleared, but now an interrupt is generated when the 9th bit is set. this allows the dma to service all receptions, but also allows the cpu to intervene when the trailer (9th bit set) is received. in all modes using dma, the interrupts other than transmitter ready and character received interrupts can still be generated. this allows the dma to handle the standard sending and receiving characters while the cpu can intervene when a non-standard event (e.g., framing error) occurs. option to boot from 8- or 16-bit memory the am186ed/edlv microcontrollers can boot from 8- or 16-bit-wide non-volatile memory, based on the state of the s 2/btsel pin. if s 2/btsel is pulled high or left floating, an internal pullup sets the boot mode option to 16-bit. if s 2/btsel is pulled resistively low during reset, the boot mode option is for 8-bit. the status of the s 2/btsel pin is latched on the rising edge of reset. if the 8-bit boot option is selected, the width of the memory region associated with ucs can be changed in the auxcon register. this allows for cheaper 8-bit- wide memory to be used for booting the microcontroller, while speed-critical code and data can be executed from 16-bit-wide lower memory. eight-bit or 16-bit-wide peripherals can be used in the memory area between lcs and ucs or in the i/o space. the entire memory map can be set to 16-bit or 8-bit or mixed between 8-bit and 16-bit based on the usiz, lsiz, msiz, and iosiz bits in the auxcon register. improved external bus master support when the bus is arbitrated away from the am186ed/ edlv microcontrollers using the hold pin, the chip selects are driven high (negated) and then held high with an internal ~10-kohm pullup. this allows external bus masters to assert the chip selects by externally pulling them low, without having to combine the chip selects from the am186ed/edlv microcontrollers and the external bus master in logic external to the am186ed/edlv microcontrollers. this internal pullup is activated for any bus arbitration, even if the pin is being used as a pio input. psram controller removed the psram mode found on the am186es/eslv microcontrollers has been removed and replaced with a dram controller. this includes removal of the variant psram lcs timing and refresh strobe on mcs 3.
14 am186ed/edlv microcontrollers preliminary d ra f t tqfp connection diagrams and pinouts am186ed/edlv microcontrollers top side view100-pin thin quad flat pack (tqfp) note: pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ad8 2 ad1 3 ad9 4 ad2 5 ad10 6 ad3 7 ad11 8 ad4 9 ad12 10 ad5 11 12 ad13 13 ad6 14 15 ad14 16 ad7 17 ad15 18 19 20 txd1 21 rxd1 22 23 rxd0 24 txd0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0/int5 99 drq1/int6 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq rts0/rtr0 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0/ras 0 /1 2/lcas 3/ gnd gnd gnd gnd gnd whb wlb dt/r den /ds mcs 0 mcs 1/ucas bhe/aden wr rd s2/btsel s1 s0 inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs ras1 res lcs s6/c lkdiv 2 uzi cts 0/enrx 0 /pwd /rts1/rtr1 /cts1/enrx1 am186ed/edlv microcontrollers
am186ed/edlv microcontrollers 15 preliminary d ra f t tqfp pin designationsam186ed/edlv microcontrollers sorted by pin number pin no. name pin no. name pin no. name pin no. name 1ad0 26 rts 0/rtr 0/ pio20 51 a11 76 int3/inta 1/irq 2 ad8 27 bhe /aden 52 a10 77 int2/inta 0/pwd/ pio31 3ad1 28wr 53 a9 78 int1/select 4 ad9 29 rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs /once 1 6 ad10 31 ardy 56 a6 81 lcs /once 0/ ras 0 7ad3 32s 2/btsel 57 a5 82 pcs 6/a2/pio2 8ad11 33s 1 58a4 83pcs 5/a1/pio3 9ad4 34s 0 59a3 84v cc 10 ad12 35 gnd 60 a2 85 pcs 3/rts 1/ rtr 1/ pio19 11ad5 36x1 61v cc 86 pcs 2/cts 1/ enrx 1/pio18 12gnd 37x2 62a1 87gnd 13 ad13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 whb 90 v cc 16 ad14 41 gnd 66 wlb 91 mcs 2/lcas / pio24 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/ras 1/ pio25 18 ad15 43 a18/pio8 68 hold 93 gnd 19 s6/clkdiv 2/pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd1/pio27 46 a16 71 dt/r/ pio4 96 tmrout1/pio1 22 rxd1/pio28 47 a15 72 den /ds /pio5 97 tmrout0/pio10 23 cts 0/enrx 0/pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 rxd0/pio23 49 a13 74 mcs 1/ucas / pio15 99 drq1/int6/pio13 25 txd0/pio22 50 a12 75 int4/pio30 100 drq0/int5/pio12
16 am186ed/edlv microcontrollers preliminary d ra f t tqfp pin designationsam186ed/edlv microcontrollers sorted by pin name pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 87 rxd1 22 a1 62 ad6 14 gnd 93 s 034 a2 60 ad7 17 hlda 67 s 133 a3 59 ad8 2 hold 68 s 2/btsel 32 a4 58 ad9 4 int0 79 s6/c lkdiv 2/ pio29 19 a5 57 ad10 6 int1/select 78 srdy/pio6 69 a6 56 ad11 8 int2/inta 0/pwd/ pio31 77 tmrin0/pio11 98 a7 55 ad12 10 int3/inta 1/irq 76 tmrin1/pio0 95 a8 54 ad13 13 int4/pio30 75 tmrout0/ pio10 97 a9 53 ad14 16 lcs /once 0/ras 0 81 tmrout1/pio1 96 a10 52 ad15 18 mcs 0/pio14 73 txd0/pio22 25 a11 51 ale 30 mcs 1/ucas / pio15 74 txd1 21 a12 50 ardy 31 mcs 2/lcas /pio24 91 ucs /once 180 a13 49 bhe /aden 27 mcs 3/ras 1/pio25 92 uzi /pio26 20 a14 48 clkouta 39 nmi 70 v cc 15 a15 47 clkoutb 40 pcs 0/pio16 89 v cc 38 a16 46 cts 0/enrx 0/ pio21 23 pcs 1/pio17 88 v cc 44 a17/pio7 45 den /ds /pio5 72 pcs 2/cts 1/ enrx 1/pio18 86 v cc 61 a18/pio8 43 drq0/int5/pio12 100 pcs 3/rts 1/rtr 1/ pio19 85 v cc 84 a19/pio9 42 drq1/int6/pio13 99 pcs 5/a1/pio3 83 v cc 90 ad0 1 dt/r /pio4 71 pcs 6/a2/pio2 82 whb 65 ad1 3 gnd 12 rd 29 wlb 66 ad2 5 gnd 35 res 94 wr 28 ad3 7 gnd 41 rts 0/rtr 0/pio20 26 x1 36 ad4 9 gnd 64 rxd0/pio23 24 x2 37
am186ed/edlv microcontrollers 17 preliminary d ra f t pqfp connection diagrams and pinouts am186ed/edlv microcontrollers top side view100-pin plastic quad flat pack (pqfp) note: pin 1 is marked for orientation. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 txd1 rxd1 cts0/enrx0 rxd0 txd0 gnd gnd ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/c lkdiv 2 v cc v cc am186ed/edlv microcontrollers 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 bhe /aden uzi whb wlb den/ds mcs0 wr rd s 2/btsel s 1 s 0 mcs 1/ucas int3/inta 1/irq int2/inta 0/pwd int1/select ucs /once 1 lcs /once 0/ras 0 pcs 6/a2 pcs 5/a1 pcs 3/rts 1/rtr 1 pcs 2/cts 1/enrx 1 pcs 1 pcs 0 mcs 2/lcas mcs 3/ras 1 res rts 0/rtr 0 drq1/int6 drq0/int5
18 am186ed/edlv microcontrollers preliminary d ra f t pqfp pin designationsam186ed/edlv microcontrollers sorted by pin number pin no. name pin no. name pin no. name pin no. name 1 rxd0/pio23 26 a13 51 mcs 1/ucas /pio15 76 drq1/int6/pio13 2 txd0/pio22 27 a12 52 int4/pio30 77 drq0/int5/pio12 3 rts 0/rtr 0/ pio20 28 a11 53 int3/inta 1/irq 78 ad0 4bhe /aden 29 a10 54 int2/inta 0/pwd/ pio31 79 ad8 5wr 30 a9 55 int1/select 80 ad1 6rd 31 a8 56 int0 81 ad9 7 ale 32 a7 57 ucs /once 182ad2 8 ardy 33a6 58lcs /once 0/ras 083ad10 9s 2/btsel 34a5 59pcs 6/a2/pio2 84 ad3 10 s 1 35a4 60pcs 5/a1/pio3 85 ad11 11 s 0 36a3 61v cc 86 ad4 12 gnd 37 a2 62 pcs 3/rts 1/rtr 1/ pio19 87 ad12 13 x1 38 v cc 63 pcs 2/cts 1/ enrx 1/pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ad13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 whb 67 v cc 92 v cc 18 gnd 43 wlb 68 mcs 2/lcas /pio24 93 ad14 19 a19/pio9 44 hlda 69 mcs 3/ras 1/pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ad15 21 v cc 46 srdy/pio6 71 res 96 s6/c lkdiv 2/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /pio26 23 a16 48 dt/r/ pio4 73 tmrout1/pio1 98 txd1/pio27 24 a15 49 den /ds /pio5 74 tmrout0/pio10 99 rxd1/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 cts 0/enrx 0/pio21
am186ed/edlv microcontrollers 19 preliminary d ra f t pqfp pin designationsam186ed/edlv microcontrollers sorted by pin name pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 70 rxd1/pio28 99 a1 39 ad6 91 gnd 89 s 011 a2 37 ad7 94 hlda 44 s 110 a3 36 ad8 79 hold 45 s 2/btsel 9 a4 35 ad9 81 int0 56 s6/c lkdiv 2/ pio29 96 a5 34 ad10 83 int1/select 55 srdy/pio6 46 a6 33 ad11 85 int2/inta 0/ pwd/pio31 54 tmrin0/pio11 75 a7 32 ad12 87 int3/inta 1/irq 53 tmrin1/pio0 72 a8 31 ad13 90 int4/pio30 52 tmrout0/ pio10 74 a9 30 ad14 93 lcs /once 0/ras 0 58 tmrout1/pio1 73 a10 29 ad15 95 mcs 0/pio14 50 txd0/pio22 2 a11 28 ale 7 mcs 1/ucas /pio15 51 txd1/pio27 98 a12 27 ardy 8 mcs 2/lcas /pio24 68 ucs /once 157 a13 26 bhe /aden 4mcs 3/ras 1/pio25 69 uzi /pio26 97 a14 25 clkouta 16 nmi 47 v cc 15 a15 24 clkoutb 17 pcs 0/pio16 66 v cc 21 a16 23 cts 0/enrx 0/ pio21 100 pcs 1/pio17 65 v cc 38 a17/pio7 22 den /ds /pio5 49 pcs 2/cts 1/enrx 1/ pio18 63 v cc 61 a18/pio8 20 drq0/int5/pio12 77 pcs 3/rts 1/rtr 1/ pio19 62 v cc 67 a19/pio9 19 drq1/int6/pio13 76 pcs 5/a1/pio3 60 v cc 92 ad0 78 dt/r /pio4 48 pcs 6/a2/pio2 59 whb 42 ad1 80 gnd 12 rd 6wlb 43 ad2 82 gnd 18 res 71 wr 5 ad3 84 gnd 41 rts 0/rtr 0/pio20 3 x1 13 ad4 86 gnd 64 rxd0/pio23 1 x2 14
20 am186ed/edlv microcontrollers preliminary d ra f t logic symbolam186ed/edlv microcontrollers notes: * these signals are the normal function of a pin that can be used as a pio. see pin descriptions beginning on page 21 and table 2 on page 29 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb a19Ca0 ad15Cad0 ale whb wlb rd wr s 1Cs 0 hold hlda dt/r den /ds ardy srdy tmrin0 tmrout0 20 16 clocks address and address/data buses bus control timer control res int4 int3/inta 1/irq int2/inta 0/pwd int1/select int0 nmi pcs 6/a2 pcs 5/a1 pcs 1Cpcs 0 lcs /once 0/ras 0 mcs 2/lcas ucs /once 1 drq0/int5 pio32Cpio0 2 32 shared reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 2 tmrin1 tmrout1 mcs 3/ras 1 s6/c lkdiv 2 bhe /aden uzi ** * * * * * * * * * * * * * * * * * * drq1/int6 drq0/int5 drq1/int6 * txd0 rxd0 * * cts 0/enrx 0 rts 0/rtr 0 * * txd1 rxd1 * * pcs 2/cts 1/enrx 1 pcs 3/rts 1/rtr 1 pcs 3/rts 1/rtr 1 * pcs 2/cts 1/enrx 1 * * * s 2/btsel mcs 1/ucas * mcs 0 *
am186ed/edlv microcontrollers 21 preliminary d ra f t pin descriptions pins that are used by emulators the following pins are used by emulators: a19Ca0, ad7Cad0, ale, bhe /ad en , clkouta, rd , s 2Cs 0, s6/c lkdiv 2, and uzi . many emulators require s6/clkdiv 2 and uzi to be configured in their normal functionality as s6 and uzi , not as pios. if bhe /aden is held low during the rising edge of res , s6 and uzi are configured in their normal functionality. pin terminology the following terms are used to describe the pins: input an input-only pin. output an output-only pin. input/output a pin that can be either input or output (i/o). synchronous synchronous inputs must meet setup and hold times in relation to clkouta. synchronous outputs are synchronous to clkouta. asynchronous inputs or outputs that are asynchronous to clkouta. a19Ca0 (a19/pio9, a18/pio8, a17/pio7) address bus (output, three-state, synchronous) these pins supply nonmultiplexed memory or i/o addresses to the system one half of a clkouta period earlier than the multiplexed address and data bus (ad15Cad0). during a bus hold or reset condition, the address bus is in a high-impedance state. while the am186ed/edlv microcontrollers are directly connected to dram, a19Ca0 will serve as the nonmultiplexed address bus for sram, flash, prom, eprom, and peripherals. the odd address pins (a17, a15, a13, a11, a9, a7, a5, a3, and a1) will have both the row and column address during a dram space access. the odd address signals connect directly to the row and column multiplexed address bus of the dram. the even address pins (a18, a16, a14, a12, a10, a8, a6, a4, a2, and a0) and a19 will have the initial address asserted during the full dram access. these signals will not transition during a dram access. ad15Cad8 address and data bus (input/output, three-state, synchronous, level-sensitive) ad15Cad8 these time-multiplexed pins supply memory or i/o addresses and data to the system. this bus can supply an address to the system during the first period of a bus cycle (t 1 ). it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when whb is deasserted, these pins are three-stated during t 2 , t 3 , and t 4. during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0) can also be used to load system configuration information into the internal reset configuration register. when accesses are made to 8-bit-wide memory regions, ad15Cad8 drive their corresponding address signals throughout the access. if the disable address phase and 8-bit mode are selected (see the aden description with the bhe /aden pin), then ad15Cad8 are three-stated during t 1 and driven with their corresponding address signal from t 2 to t 4 . ad7Cad0 address and data bus (input/output, three-state, synchronous, level-sensitive) these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. this bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t 1 ), and it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). in 8-bit mode, ad7C ad0 supplies the data for both high and low bytes. the address phase of these pins can be disabled. see the aden pin description with the bhe /aden pin. when wlb is deasserted, these pins are three-stated during t 2 , t 3 , and t 4. during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0) can also be used to load system configuration information into the internal reset configuration register. ale address latch enable (output, synchronous) this pin indicates to the system that an address ap- pears on the address and data bus (ad15Cad0). the address is guaranteed to be valid on the trailing edge of ale. this pin is three-stated during once mode. ale is three-stated and held resistively low during a bus hold condition. in addition, ale has a weak internal pulldown resistor that is active during reset, so that an external device does not get a spurious ale during reset.
22 am186ed/edlv microcontrollers preliminary d ra f t ardy asynchronous ready (input, asynchronous, level-sensitive) this pin is a true asynchronous ready that indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the ardy pin is asynchronous to clkouta and is active high. to guarantee the number of wait states inserted, ardy or srdy must be synchronized to clkouta. if the falling edge of ardy is not synchronized to clkouta as specified, an additional clock period can be added. to always assert the ready condition to the microcontroller, tie ardy high. if the system does not use ardy, tie the pin low to yield control to srdy. bhe /aden bus high enable (three-state, output, synchronous) address enable (input, internal pullup) bhe during a memory access, this pin and the least- significant address bit (ad0 or a0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe /aden and ad0 pins are encoded as shown in table 1. table 1. data byte encoding bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not need to be latched. bhe floats during bus hold and reset. wlb and whb implement the functionality of bhe and ad0 for high and low byte-write enables. ucas and lcas implement high and low-byte selection for dram devices. bhe /aden also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a refresh cycle is indicated when both bhe /aden and ad0 are high. during refresh cycles, the a bus is indeterminate and the ad bus is driven to ffffh during the address phase of the ad bus cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. aden if bhe /aden is held high or left floating during power-on reset, the address portion of the ad bus (ad15Cad0) is enabled or disabled during lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the ad bus will not drive the address during t 1 . there is a weak internal pullup resistor on bhe /aden so no external pullup is required. disabling the address phase reduces power consumption. if bhe /aden is held low on power-on reset, the ad bus drives both addresses and data, regardless of the da bit setting. the pin is sampled on the rising edge of res . (s6 and uzi also assume their normal functionality in this instance. see table 2 on page 29.) the internal pullup on aden is ~9 kohm. note: for 8-bit accesses, ad15Cad8 are driven with addresses during the t 2 Ct 4 bus cycle, regardless of the setting of the da bit in the umcs and lmcs registers. clkouta clock output a (output, synchronous) this pin supplies the internal clock to the system. depending on the value of the system configuration register (syscon), clkouta operates at either the pll frequency (x1), the power-save frequency, or is held low. clkouta remains active during reset and bus hold conditions. all ac timing specs that use a clock relate to clkouta. clkoutb clock output b (output, synchronous) this pin supplies an additional clock with a delayed output compared to clkouta. depending upon the value of the system configuration register (syscon), clkoutb operates at either the pll frequency (x1), the power-save frequency, or is held low. clkoutb remains active during reset and bus hold conditions. clkoutb is not used for ac timing specs. cts 0/enrx 0/pio21 clear-to-send 0 (input, asynchronous) enable-receiver-request 0 (input, asynchronous) cts 0 this pin provides the clear-to-send signal for asynchronous serial port 0 when the enrx0 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the cts 0 signal gates the transmission of data from the associated serial port transmit register. when cts 0 is asserted, the transmitter begins transmission of a frame of data, if any is available. if cts 0 is deasserted, the transmitter holds the data in the serial port transmit register. the value of cts 0 is checked only at the beginning of the transmission of the frame. enrx 0 this pin provides the enable receiver request for asynchronous serial port 0 when the enrx0 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial bhe ad0 type of bus cycle 00word transfer 01 high byte transfer (bits 15C8) 1 0 low byte transfer (bits 7C0) 11reserved
am186ed/edlv microcontrollers 23 preliminary d ra f t port 0 control register is set). the enrx 0 signal enables the receiver for the associated serial port. den /ds /pio5 data enable (output, three-state, synchronous) data strobe (output, three-state, synchronous) den this pin supplies an output enable to an external data-bus transceiver. den is asserted during memory, i/o, and interrupt acknowledge cycles. den is deasserted when dt/r changes state. den floats during a bus hold or reset condition. ds the data strobe provides a signal where the write cycle timing is identical to the read cycle timing. when used with other control signals, ds provides an interface for 68k-type peripherals without the need for additional system interface logic. when ds is asserted, addresses are valid. when ds is asserted on writes, data is valid. when ds is asserted on reads, data can be asserted on the ad bus. note: this pin resets to den . drq0/int5/pio12 dma request 0 (input, synchronous, level-sensitive) maskable interrupt request 5 (input, asynchronous, edge-triggered) drq0 this pin indicates to the microcontroller that an external device is ready for dma channel 0 to perform a transfer. drq0 is level-triggered and internally synchronized. drq0 is not latched and must remain active until serviced. int5 if dma 0 is not enabled or dma 0 is not being used with external synchronization, int5 can be used as an additional external interrupt request. int5 shares the dma 0 interrupt type (0ah) and register control bits. int5 is edge-triggered only and must be held until the interrupt is acknowledged. drq1/int6/pio13 dma request 1 (input, synchronous, level-sensitive) maskable interrupt request 6 (input, asynchronous, edge-triggered) drq1 this pin indicates to the microcontroller that an external device is ready for dma channel 1 to perform a transfer. drq1 is level-triggered and internally synchronized. drq1 is not latched and must remain active until serviced. int6 if dma 1 is not enabled or dma 1 is not being used with external synchronization, int6 can be used as an additional external interrupt request. int6 shares the dma 1 interrupt type (0bh) and register control bits. int6 is edge-triggered only and must be held until the interrupt is acknowledged. dt/r /pio4 data transmit or receive (output, three-state, synchronous) this pin indicates in which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the microcontroller transmits data. when this pin is deasserted low, the microcontroller receives data. dt/r floats during a bus hold or reset condition. gnd ground ground pins connect the microcontroller to the system ground. hlda bus hold acknowledge (output, synchronous) this pin is asserted high to indicate to an external bus master that the microcontroller has released control of the local bus. when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress. it then relinquishes control of the bus to the external bus master by asserting hlda and floating den , rd , wr , s 2Cs 0, ad15Cad0, s6, a19Ca0, bhe , whb , wlb , and dt/r . the following chip selects are three-stated (then will be held high with an ~10-kohm resistor): ucs , lcs , mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0, ras 0, ras 1, ucas , and lcas . ale is also three- stated (then will be held low with an ~10-kohm resistor). when the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting hold. the microcontroller responds by deasserting hlda. if the microcontroller requires access to the bus (for example, to refresh), it will deassert hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the microcontroller access to the bus. see the timing diagrams for bus hold on page 86. hold bus hold request (input, synchronous, level-sensitive) this pin indicates to the microcontroller that an external bus master needs control of the local bus. the am186ed/edlv microcontrollers hold latency time, that is, the time between hold request and hold acknowledge, is a function of the activity occur- ring in the processor when the hold request is re- ceived. a hold request is second only to dram
24 am186ed/edlv microcontrollers preliminary d ra f t refresh requests in priority of activity requests received by the processor. for more information, see the hlda pin description on page 23. int0 maskable interrupt request 0 (input, asynchronous) this pin indicates to the microcontroller that an interrupt request has occurred. if the int0 pin is not masked, the microcontroller transfers program execution to the location specified by the int0 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int0 until the request is acknowledged. int1/select maskable interrupt request 1 (input, asynchronous) slave select (input, asynchronous) int1 this pin indicates to the microcontroller that an interrupt request has occurred. if int1 is not masked, the microcontroller transfers program execution to the location specified by the int1 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int1 until the request is acknowledged. select when the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. the int0 pin must indicate to the microcontroller that an interrupt has occurred before the select pin indicates to the microcontroller that the interrupt type appears on the bus. int2/inta 0/pwd/pio31 maskable interrupt request 2 (input, asynchronous) interrupt acknowledge 0 (output, synchronous) pulse width demodulator (input, schmitt trigger) int2 this pin indicates to the microcontroller that an interrupt request has occurred. if the int2 pin is not masked, the microcontroller transfers program execution to the location specified by the int2 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int2 until the request is acknowledged. int2 becomes inta 0 when int0 is configured in cascade mode. inta 0 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int0. the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. pwd if pulse width demodulation is enabled, pwd processes a signal through the schmitt trigger. pwd is used internally to drive timerin0 and int2, and pwd is inverted internally to drive timerin1 and int4. if int2 and int4 are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating pwd signal can be calculated by comparing the values in timer 0 and timer 1. in pwd mode, the signals timerin0/pio11, timerin1/pio0, and int4/pio30 can be used as pios. if they are not used as pios, they are ignored internally. the level of int2/inta 0/pwd/pio31 is reflected in the pio data register for pio31 as if it was a pio. int3/inta 1/irq maskable interrupt request 3 (input, asynchronous) interrupt acknowledge 1 (output, synchronous) slave interrupt request (output, synchronous) int3 this pin indicates to the microcontroller that an interrupt request has occurred. if the int3 pin is not masked, the microcontroller then transfers program execution to the location specified by the int3 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int3 until the request is acknowledged. int3 becomes inta 1 when int1 is configured in cascade mode. inta 1 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int1. the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. irq when the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller.
am186ed/edlv microcontrollers 25 preliminary d ra f t int4/pio30 maskable interrupt request 4 (input, asynchronous) this pin indicates to the microcontroller that an interrupt request has occurred. if the int4 pin is not masked, the microcontroller then transfers program execution to the location specified by the int4 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int4 until the request is acknowledged. when pulse width demodulation mode is enabled, the int4 signal is used internally to indicate a high-to-low transition on the pwd signal. when pulse width demodulation mode is enabled, int4/pio30 can be used as a pio. lcs /once 0/ras 0 lower memory chip select (output, synchronous, internal pullup) once mode request 0 (input) row address strobe 0 lcs this pin indicates to the system that a memory access is in progress to the lower memory block. the base address and size of the lower memory block are programmable up to 512 kbytes. lcs is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. lcs is three-stated and held resistively high during a bus hold condition. in addition, lcs has an ~9-kohm internal pullup resistor that is active during reset. once 0 during reset, this pin and once 1 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode; otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the microcontroller does not inadvertently enter once mode, once 0 has a weak internal pullup resistor that is active only during reset. r as 0 this pin is the row address strobe for the lower dram block. the selection of ras 0 or lcs functionality, along with their configurations, are set using the lmcs register. ras 0 is three-stated and held resistively high during a bus hold condition. in addition, ras 0 has a weak internal pullup resistor that is active during reset. mcs 0/pio14 midrange memory chip select 0 (output, synchronous, internal pullup) this pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 0 can be programmed as the chip select for the entire middle chip select address range. this mode is recommended when using dram since the mcs 1, mcs 2, and mcs 3 chip selects function as ras and cas signals for the dram interface and are not available as chip selects. mcs 0 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. mcs 0 is three-stated and held resistively high during a bus hold condition. in addition, mcs 0 has a weak internal pullup resistor that is active during reset. mcs 1/ucas /pio15 midrange memory chip select (output, synchronous, internal pullup) upper column address strobe this pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 1 is configured for 8-bit or 16-bit bus size via the auxiliary configuration register. mcs 1 is three-stated and held resistively high during a bus hold condition. in addition, mcs 1 has a weak internal pullup resistor that is active during reset. if mcs 0 is programmed to be active for the entire middle chip-select range, then this signal is available as a pio or a dram control. if this signal is not programmed as a pio or dram control and if mcs 0 is programmed for the entire middle chip-select range, this signal operates normally. ucas when either bank of dram is activated, the ucas functionality is enabled. the ucas activates when the dram access is for the ad15Cad8 byte. ucas also activates at the start of a dram refresh access. ucas is three-stated and held resistively high during a bus hold condition. in addition, ucas has a weak internal pullup resistor that is active during reset. mcs 2/lcas /pio24 midrange memory chip select (output, synchronous, internal pullup) lower column address strobe this pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of
26 am186ed/edlv microcontrollers preliminary d ra f t the midrange memory block are programmable. mcs 2 is configured for 8-bit or 16-bit bus size via the auxiliary configuration register. mcs 2 is three-stated and held resistively high during a bus hold condition. in addition, it has a weak internal pullup resistor that is active during reset. if mcs 0 is programmed to be active for the entire middle chip-select range, then this signal is available as a pio or a dram control. if this pin is not programmed as a pio or dram control and if mcs 0 is programmed for the whole middle chip-select range, this signal operates normally. lcas when either bank of dram is activated, the lcas functionality is enabled. the lcas activates when the dram access is for th e ad7Cad0 byte. lcas also activates at the start of a dram refresh access. lcas is three-stated and held resistively high during a bus hold condition. in addition, lcas has a weak internal pullup resistor that is active during reset. mcs 3/ras 1/pio25 midrange memory chip select 3 (output, synchronous, internal pullup) row address strobe 1 (output, synchronous) mcs 3 this pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. the base address and size of the mid-range memory block are programmable. mcs 3 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. mcs 3 is three-stated and held resistively high during a bus hold condition. in addition, this pin has a weak internal pullup resistor that is active during reset. if mcs 0 is programmed for the entire middle chip- select range, then this signal is available as a pio or a dram control. if mcs 3 is not programmed as a pio or dram control and if mcs 0 is programmed for the entire middle chip-select range, this signal operates normally. ras 1 this pin is the row address strobe for the upper dram block. the selection of ras 1 or ucs functionality, along with their configurations, are set using the umcs register. when ras 1 is activated, the code activating ras 1 must not reside in the ucs memory block. when ras 1 is activated, ucs is automatically deactivated and remains negated. ras 1 is three-stated and held resistively high during a bus hold condition. in addition, ras 1 has a weak internal pullup resistor that is active during reset. nmi nonmaskable interrupt (input, synchronous, edge-sensitive) this pin indicates to the microcontroller that an interrupt request has occurred. the nmi signal is the highest priority hardware interrupt and, unlike the int6Cint0 pins, cannot be masked. the microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when nmi is asserted. although nmi is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request registers. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the if (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable interrupts are re-enabled by software in the nmi interrupt service routine, via the sti instruction for example, the fact that an nmi is currently in service does not have any effect on the priority resolution of maskable interrupt requests. for this reason, it is strongly advised that the interrupt service routine for nmi should not enable the maskable interrupts. an nmi transition from low to high is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the interrupt is recognized, the nmi pin must be asserted for at least one clkouta period. pcs 1/pio17, pcs 0/pio16 peripheral chip selects (output, synchronous) these pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs chip selects can overlap either block of dram. the pcs chip selects must have the same or greater number of wait states as the bank of dram they overlap. the pcs signals take precedence over dram accesses when dram and memory-mapped peripherals overlap. pcs 1Cpcs 0 are three-stated and held resistively high during a bus hold condition. in addition, pcs 1Cpcs 0 each have a weak internal pullup resistor that is active during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range
am186ed/edlv microcontrollers 27 preliminary d ra f t covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 0Cpcs 1 also have extended wait state options. pcs 2/cts 1/enrx 1/pio18 peripheral chip select 2 (output, synchronous) clear-to-send 1 (input, asynchronous) enable-receiver-request 1 (input, asynchronous) pcs 2 this pin provides the peripheral chip select 2 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. the pcs 2 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs chip selects can overlap either block of dram. the pcs chip selects must have the same or greater number of wait states as the bank of dram they overlap. the pcs signals take precedence over dram accesses when dram and memory-mapped peripherals overlap. pcs 2 is three-stated and held resistively high during a bus hold condition. in addition, pcs 2 has a weak internal pullup resistor that is active during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 2 also has extended wait state options. cts 1 this pin provides the clear-to-send signal for asynchronous serial port 1 when the enrx1 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the cts 1 signal gates the transmission of data from the associated serial port transmit register. when cts 1 is asserted, the transmitter begins transmission of a frame of data, if any is available. if cts 1 is deasserted, the transmitter holds the data in the serial port transmit register. the value of cts 1 is checked only at the beginning of the transmission of the frame. enrx 1 this pin provides the enable receiver request for asynchronous serial port 1 when the enrx1 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the enrx 1 signal enables the receiver for the associated serial port. pcs 3/rts 1/rtr 1/pio19 peripheral chip select 3 (output, synchronous) ready-to-send 1 (output, asynchronous) ready-to-receive 1 (output, asynchronous) pcs 3 this pin provides the peripheral chip select 3 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. the pcs 3 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs chip selects can overlap either block of dram. the pcs chip selects must have the same or greater number of wait states as the bank of dram they overlap. the pcs signals take precedence over dram accesses when dram and memory-mapped peripherals overlap. pcs 3 is three-stated and held resistively high during a bus hold condition. in addition, pcs 3 has a weak internal pullup resistor that is active during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 3 also has extended wait state options. rts 1 this pin provides the ready-to-send signal for asynchronous serial port 1 when the rts 1 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the rts 1 signal is asserted when the associated serial port transmit register contains data which has not been transmitted. rtr 1 this pin provides the ready-to-receive signal for asynchronous serial port 1 when the rts 1 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the rtr 1 signal is asserted when the associated serial port receive register does not contain valid, unread data. pcs 5/a1/pio3 peripheral chip select 5 (output, synchronous) latched address bit 1 (output, synchronous) pcs 5 this pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs chip selects can overlap either block of dram. the pcs chip selects must have the same or greater number of wait states as the bank of dram
28 am186ed/edlv microcontrollers preliminary d ra f t they overlap. the pcs signals take precedence over dram accesses when dram and memory-mapped peripherals overlap. pcs 5 is three-stated and held resistively high during a bus hold condition. in addition, pcs 5 has a weak internal pullup resistor that is active during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 5 also has extended wait state options. a1 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched address bit 1 to the system. during a bus hold condition, a1 retains its previously latched value. pcs 6/a2/pio2 peripheral chip select 6 (output, synchronous) latched address bit 2 (output, synchronous) pcs 6 this pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs chip selects can overlap either block of dram. the pcs chip selects must have the same or greater number of wait states as the bank of dram they overlap. the pcs signals take precedence over dram accesses when dram and memory-mapped peripherals overlap. pcs 6 is three-stated and held resistively high during a bus hold condition. in addition, pcs 6 has a weak internal pullup resistor that is active during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 6 also has extended wait state options. a2 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched address bit 2 to the system. during a bus hold condition, a2 retains its previously latched value. pio31Cpio0 (shared) programmable i/o pins (input/output, asynchronous, open-drain) the am186ed/edlv microcontrollers provide 32 individually programmable i/o pins. each pio can be programmed with the following attributes: pio function (enabled/disabled), direction (input/output), and weak pullup or pulldown. the pins that are multiplexed with pio31Cpio0 are listed in table 2 and table 3. after power-on reset, the pio pins default to various configurations. the column titled power-on reset status in table 2 and table 3 lists the defaults for the pios. most of the pio pins are configured as pio inputs with pullup after power-on reset. the system initialization code must reconfigure any pio pins as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. pio15 and pio24 should be set to normal operation before enabling either bank of dram. pio25 should be set to normal operation before enabling the upper bank of dram. rd read strobe (output, synchronous, three-state) rd this pin indicates to the system that the microcontroller is performing a memory or i/o read cycle. rd is guaranteed to not be asserted before the address and data bus is floated during the address-to- data transition. rd floats during a bus hold condition. res reset (input, asynchronous, level-sensitive) this pin requires the microcontroller to perform a reset. when res is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and transfers cpu control to the reset address, ffff0h. res must be held low for at least 1 ms. res can be asserted asynchronously to clkouta because res is synchronized internally. for proper initialization, v cc must be within specifications, and clkouta must be stable for more than four clkouta periods during which res is asserted. the microcontroller begins fetching instructions approximately 6.5 clkouta periods after res is deasserted. this input is provided with a schmitt trigger to facilitate power-on res generation via an rc network.
am186ed/edlv microcontrollers 29 preliminary d ra f t table 2. numeric pio pin designations table 3. alphabetic pio pin designations notes: the following notes apply to both tables. 1. these pins are used by many emulators. (emulators also use s 2Cs 0, res , nmi, clkouta, bhe , ale, ad15C ad0, and a16Ca0.) 2. these pins revert to normal operation if bhe / aden is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. pio no associated pin power-on reset status 0 tmrin1 input with pullup 1 tmrout1 input with pulldown 2pcs 6/a2 input with pullup 3pcs 5/a1 input with pullup 4 dt/r normal operation (3) 5den /ds normal operation (3) 6 srdy normal operation (4) 7 (1) a17 normal operation (3) 8 (1) a18 normal operation (3) 9 (1) a19 normal operation (3) 10 tmrout0 input with pulldown 11 tmrin0 input with pullup 12 drq0/int5 input with pullup 13 drq1/int6 input with pullup 14 mcs 0 input with pullup 15 mcs 1/ucas input with pullup 16 pcs 0 input with pullup 17 pcs 1 input with pullup 18 pcs 2/cts 1/enrx 1 input with pullup 19 pcs 3/rts 1/rtr 1 input with pullup 20 rts 0/rtr 0 input with pullup 21 cts 0/enrx 0 input with pullup 22 txd0 input with pullup 23 rxd0 input with pullup 24 mcs 2/lcas input with pullup 25 mcs 3/ras 1 input with pullup 26 (1,2) uzi input with pullup 27 txd1 input with pullup 28 rxd1 input with pullup 29 (1,2) s6/c lkdiv 2 input with pullup 30 int4 input with pullup 31 int2/inta 0/pwd input with pullup associated pin pio no power-on reset status a17 (1) 7 normal operation (3) a18 (1) 8 normal operation (3) a19 (1) 9 normal operation (3) cts 0/enrx 0 21 input with pullup den /ds 5 normal operation (3) drq0/int5 12 input with pullup drq1/int6 13 input with pullup dt/r 4 normal operation (3) int2/inta 0/pwd 31 input with pullup int4 30 input with pullup mcs 0 14 input with pullup mcs 1/ucas 15 input with pullup mcs 2/lcas 24 input with pullup mcs 3/ras 1 25 input with pullup pcs 0 16 input with pullup pcs 1 17 input with pullup pcs 2/cts 1/enrx 1 18 input with pullup pcs 3/rts 1/rtr 1 19 input with pullup pcs 5/a1 3 input with pullup pcs 6/a2 2 input with pullup rts 0/rtr 0 20 input with pullup rxd0 23 input with pullup rxd1 28 input with pullup s6/c lkdiv 2 (1,2) 29 input with pullup srdy 6 normal operation (4) tmrin0 11 input with pullup tmrin1 0 input with pullup tmrout0 10 input with pulldown tmrout1 1 input with pulldown txd0 22 input with pullup txd1 27 input with pullup uzi (1,2) 26 input with pullup
30 am186ed/edlv microcontrollers preliminary d ra f t rts 0/rtr 0/pio20 ready-to-send 0 (output, asynchronous) ready-to-receive 0 (output, asynchronous) rts 0 this pin provides the ready-to-send signal for asynchronous serial port 0 when the rts 0 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the rts 0 signal is asserted when the associated serial port transmit register contains data that has not been transmitted. rtr 0 this pin provides the ready-to-receive signal for asynchronous serial port 0 when the rts 0 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the rtr 0 signal is asserted when the associated serial port receive register does not contain valid, unread data. rxd0/pio23 receive data 0 (input, asynchronous) this pin supplies asynchronous serial receive data from the system to asynchronous serial port 0. rxd1/pio28 receive data 1 (input, asynchronous) this pin supplies asynchronous serial receive data from the system to asynchronous serial port 1. s 2/btsel bus cycle status (output, three-state, synchronous) boot mode select s 2 this pin indicates to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/o indicator. s 2Cs 0 float during bus hold and hold acknowledge conditions. the s 2Cs 0 pins are encoded as shown in table 4. btsel the am186ed/edlv microcontrollers can boot from 8- or 16-bit wide nonvolatile memory, based on the state of the btsel pin. if btsel is pulled high or left floating, an internal pullup sets the boot mode option to 16-bit. if btsel is pulled resistively low during reset, the 8-bit boot mode option is selected. the status of the btsel pin is latched on the rising edge of reset. if 8-bit mode is selected, the width of the memory region associated with ucs can be changed in the auxcon register. this signal should never be tied to v cc or v ss directly since this pin is driven during normal operation. this signal should be tied low with an external resistor if the 8-bit boot mode is to be used. the internal pullup resistor on btsel is ~9 kohm. s 1Cs 0 bus cycle status (output, three-state, synchronous) these pins indicate to the system the type of bus cycle in progress. s 1 can be used as a data transmit or receive indicator. s 1Cs 0 float during bus hold and hold acknowledge conditions. the s 2Cs 0 pins are encoded as shown in table 4. table 4. bus cycle encoding s6/clkdiv 2/pio29 bus cycle status bit 6 (output, synchronous) clock divide by 2 (input, internal pullup) s6 during the second and remaining periods of a cycle (t 2 , t 3 , and t 4 ), this pin is asserted high to indicate a dma-initiated bus cycle. during a bus hold or reset condition, s6 floats. c lkdiv 2 if s6/clkdiv 2/pio29 is held low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. if this mode is selected, the pll is disabled. the pin is sampled on the rising edge of res . if s6 is to be used as pio29 in input mode, the device driving pio29 must not drive the pin low during power- on reset. s6/clkdiv 2/pio29 defaults to a pio input with pullup, so the pin does not need to be driven high externally. srdy/pio6 synchronous ready (input, synchronous, level-sensitive) this pin indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active high input synchronized to clkouta. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to always assert the ready condition to the s 2/btsel s 1s 0 bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 write data to i/o 011halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive)
am186ed/edlv microcontrollers 31 preliminary d ra f t microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. tmrin0/pio11 timer input 0 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 0. after internally synchronizing a low-to-high transition on tmrin0, the microcontroller increments the timer. tmrin0 must be tied high if not being used. when pio11 is enabled, tmrin0 is pulled high internally. tmrin0 is driven internally by int2/inta 0/pwd when pulse width demodulation mode is enabled. the tmrin0/pio11 pin can be used as a pio when pulse width demodulation mode is enabled. tmrin1/pio0 timer input 1 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 1. after internally synchronizing a low-to-high transition on tmrin1, the microcontroller increments the timer. tmrin1 must be tied high if not being used. when pio0 is enabled, tmrin1 is pulled high internally. tmrin1 is driven internally by int2/inta 0/pwd when pulse width demodulation mode is enabled. the tmrin1/pio0 pin can be used as a pio when pulse width demodulation mode is enabled. tmrout0/pio10 timer output 0 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout0 is floated during a bus hold or reset. tmrout1/pio1 timer output 1 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout1 floats during a bus hold or reset. txd0/pio22 transmit data 0 (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from serial port 0. txd1/pio27 transmit data 1 (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from serial port 1. ucs /once 1 upper memory chip select (output, synchronous) once mode request 1 (input, internal pullup) ucs this pin indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbytes. ucs is three-stated and held resistively high during a bus hold condition. in addition, ucs has an ~9-kohm internal pullup resistor that is active during reset. after reset, ucs is active for the 64 kbyte memory range from f0000h to fffffh, including the reset address of ffff0h. when ras 1 is activated, the code activating ras 1 must not reside in the ucs memory block. when ras 1 is activated, ucs is automatically deactivated and remains negated. this allows code to boot from ucs , copy its code to another memory device, then activate a dram bank in place of the u cs memory block. once 1 during reset, this pin and lcs /once 0 indi- cate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the ris- ing edge of res . if both pins are asserted low, the mi- crocontroller enters once mode. otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the micro- controller does not inadvertently enter once mode, once 1 has a weak internal pullup resistor that is ac- tive only during a reset. uzi /pio26 upper zero indicate (output, synchronous) this pin lets the designer determine if an access to the interrupt vector table is in progress by oring it with bits 15C10 of the address and data bus (ad15Cad10). uzi is the logical and of the inverted a19Ca16 bits. it asserts in the first period of a bus cycle and is held throughout the cycle. v cc power supply (input) these pins supply power (+5 v) to the microcontroller. whb write high byte (output, three-state, synchronous) this pin and wlb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 microcontroller designs, information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated.
32 am186ed/edlv microcontrollers preliminary d ra f t whb is asserted with ad15Cad8. whb is the logical or of bhe and wr . this pin floats during reset. w lb write low byte (output, three-state, synchronous) wlb this pin and whb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 microcontroller designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. wlb is asserted with ad7Cad0. wlb is the logical or of ad0 and wr . this pin floats during reset. w r write strobe (output, synchronous) wr this pin indicates to the system that the data on the bus is to be written to a memory or i/o device. wr floats during a bus hold or reset condition. wr should be used for dram write enable. x1 crystal input (input) this pin and the x2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, connect the source to the x1 pin and leave the x2 pin unconnected. x2 crystal output (output) this pin and the x1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, leave the x2 pin unconnected and connect the source to the x1 pin.
am186ed/edlv microcontrollers 33 preliminary d ra f t functional description the am186ed/edlv microcontrollers are based on the architecture of the 80c186 and 80c188 microcon- trollers. the am186ed/edlv microcontrollers function in the enhanced mode of earlier generations of 80c186 and 80c188 microcontrollers. enhanced mode in- cludes system features such as power-save control. each of the 8086, 8088, 80186, and 80188 microcon- trollers contains the same basic set of registers, in- structions, and addressing modes. the am186ed/ edlv microcontrollers are backward-compatible with the 80c186 and 80c188 microcontrollers. a full description of all the am186ed/edlv microcon- troller registers and instructions is included in the am186ed/edlv microcontrollers users manual , or- der# 21335a. memory organization memory is organized in sets of segments. each seg- ment is a linear contiguous sequence of 64k (216) 8-bit bytes. memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. the 16-bit segment values are contained in one of four internal segment registers (cs, ds, ss, or es). the physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see fig- ure 3). this allows for a 1-mbyte physical address size. all instructions that address operands in memory must specify the segment value and the 16-bit offset value. for speed and compact instruction encoding, the seg- ment register used for physical address generation is implied by the addressing mode used (see table 5). figure 3. two-component address i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. separate instructions (in, ins and out, outs) ad- dress the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero-ex- tended such that a15Ca8 are low. i/o port addresses 00f8h through 00ffh are reserved. table 5. segment register selection rules 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to memory 15 0 19 0 19 0 15 0 15 0 offset memory reference needed segment register used implicit segment selection rule instructions code (cs) instructions (including immediate data) local data data (ds) all data references stack stack (ss) all stack pushes and pops; any memory references that use bp register external data (global) extra (es) all string instruction references that use the di register as an index
34 am186ed/edlv microcontrollers preliminary d ra f t bus operation the industry-standard 80c186 and 80c188 microcon- trollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the am186ed/edlv microcontrollers continue to provide the multiplexed ad bus and, in ad- dition, provides a nonmultiplexed address (a) bus. the a bus provides an address to the system for the com- plete bus cycle (t 1 Ct 4 ). for systems where power consumption is a concern, it is possible to disable the address from being driven on the ad bus during the normal address portion of the bus cycle for accesses to ras 0, ras 1, ucs , and/or lcs address spaces. in this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. this feature is enabled through the da bits in the umcs and lmcs registers. when address disable is in effect, the number of sig- nals that assert on the bus during all normal bus cycles to the associated address space is reduced, decreas- ing power consumption and reducing processor switch- ing noise. in 8-bit mode, the address is driven on ad15Cad8 during the data portion of the bus cycle re- gardless of the setting of the da bits. if the aden pin is pulled low during processor reset, the value of the da bits in the umcs and lmcs regis- ters is ignored and the address is driven on the ad bus for all accesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed ad- dress bus and providing support for existing emulation tools. the following diagrams show the bus cycles of the am186ed/edlv microcontrollers when the address bus disable feature is in effect: figure 4 shows the affected signals during a normal read or write operation for 16-bit mode. the address and data are multiplexed onto the ad bus. figure 5 shows a 16-bit mode bus cycle when address bus disable is in effect. this results in the ad bus oper- ating in a nonmultiplexed address/data mode. the a bus has the address during a read or write operation. figure 6 shows the affected signals during a normal read or write operation for 8-bit mode. the multiplexed address/data mode is compatible with the 80c186 and 80c188 microcontrollers and might be used to take ad- vantage of existing logic or peripherals. figure 7 shows an 8-bit mode bus cycle when address bus disable is in effect. the address and data are not multiplexed. the ad7Cad0 signals have only data on the bus, while the ad bus has the address during a read or write operation. figure 4. 16-bit modenormal read and write operation clkouta t 1 t 2 t 3 t 4 ad15Cad0 (read) ad15Cad0 (write) lcs or ucs data address phase data phase a19Ca0 mcs x, pcs x note: for a detailed description of dram control signals, see dram switching characteristics beginning on page 70. or address address data address
am186ed/edlv microcontrollers 35 preliminary d ra f t figure 5. 16-bit moderead and write with address bus disable in effect figure 6. 8-bit modenormal read and write operation clkouta t 1 t 2 t 3 t 4 ad15Cad0 (write) data lcs , or ucs ad15Cad0 (read) address phase data phase a19Ca0 mcs x, pcs x note: for a detailed description of dram control signals, see dram switching characteristics beginning on page 70. or address data clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) ad15Cad8 (read or write) ad7Cad0 (write) data address phase data phase a19Ca0 lcs or ucs mcs x, pcs x or address address data address address
36 am186ed/edlv microcontrollers preliminary d ra f t figure 7. 8-bit moderead and write with address bus disable in effect bus interface unit the bus interface unit controls all accesses to external peripherals and memory devices. external accesses include those to memory devices, as well as those to memory-mapped and i/o-mapped peripherals and the peripheral control block. the am186ed/edlv micro- controllers provide an enhanced bus interface unit with the following features: n a nonmultiplexed address bus n dram address multiplexing n a static bus-sizing option for 8-bit and 16-bit mem- ory and i/o n separate byte write enables and cas for high and low bytes n data strobe bus interface option the standard 80c186/188 microcontroller multiplexed address and data bus requires system interface logic and an external address latch. on the am186ed/edlv microcontrollers, new byte write enables, dram con- trol logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. the standard 80c186/188 microcontroller required ex- ternal dram controller logic and dram address multi- plex circuitry for interfacing to dram. on the am186ed/edlv microcontrollers, the integrated dram controller and internal address multiplexing can reduce design costs by eliminating this external logic. further, system costs can be reduced for systems using more than 64k of ram by replacing sram with less expensive dram. nonmultiplexed address bus the nonmultiplexed address bus (a19Ca0) is valid one-half clkouta cycle in advance of the address on the ad bus. when used in conjunction with the modi- fied ucs and lcs outputs and the byte-write enable signals, the a19Ca0 bus provides a seamless interface to sram, and flash eprom memory systems. dram address multiplexing the a19Ca0 address bus also provides the addresses for the dram. when ras 0 or ras 1 asserts for a read or write, all the address signals are valid. this allows the dram to latch the odd addresses into the row ad- dress. before the ucas and/or lcas asserts, the odd addresses a17Ca1 change to reflect the even ad- dresses. this allows the dram to latch in the even ad- dresses into the column address. during a refresh cycle, the entire a19Ca0 address bus is stable but un- defined. the internal address and that reflected on the ad bus is all 1s. the dram pin interface is shown in table 6. clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) address ad15Cad8 lcs , or ucs ad7Cad0 (write) data address phase data phase a19Ca0 mcs x, pcs x or address data
am186ed/edlv microcontrollers 37 preliminary d ra f t table 6. dram pin interface programmable bus sizing the am186ed/edlv microcontrollers allow program- mability for data bus widths through fields in the auxil- iary configuration register (auxcon) , as shown in table 7. the usiz bit in auxcon is only configurable if the boot mode is 8-bit at reset. the width of the data access should not be modified while the processor is fetching instructions from the as- sociated address space. table 7. programming the bus width of am186ed/edlv microcontrollers note: 1. ucs width on reset is determined by the s 2/btsel pin. if ucs boots as a 16-bit space, it is not re-con- figurable to 8-bit. byte-write enables the am186ed/edlv microcontrollers provide the whb (write high byte) and wlb (write low byte) sig- nals, which act as byte-write enables. whb is the logical or of bhe and wr . whb is low when bhe and wr are both low. wlb is the logical or of a0 and wr . wlb is low when a0 and wr are both low. the byte-write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common srams. data strobe bus interface option the am186ed/edlv microcontrollers provide an asynchronous bus interface that allows the use of 68k- type peripherals. this implementation combines a ds data strobe signal (multiplexed with den ) with an asyn- chronous ardy ready input. when ds is asserted, the data and address signals are valid. a chip select signal, ardy, ds , and other control sig- nals (rd /wr ) can control the interface of 68k-type ex- ternal peripherals to the ad bus. dram interface the am186ed/edlv microcontrollers support up to two banks of dram. the use of dram can signifi- cantly reduce the memory costs for applications using more than 64k of ram. no performance is lost except for the slight overhead of periodically refreshing the dram. the lower bank of dram uses the lcs space. the upper bank of dram uses the ucs space. either, neither, or both banks can be activated. when either bank is activated, the ucas and lcas are enabled, and the dram address multiplexing is enabled on the a19Ca0 bus. when dram is activated, the corre- sponding memory bus size should be set to 16-bit. the use of 8-bit-wide dram is not supported. all refreshes to dram are 7 clocks long. the refreshes must be sep- arately enabled in the rcu. the improved memory timing specifications of the am186ed/edlv microcontrollers allow for zero-wait- state operation using 50-ns dram at a 40-mhz clock speed. 60-ns dram requires one wait state at 40 mhz and zero wait states at 33 mhz and below. 70-ns dram requires two wait states at 40 mhz, one wait state at 33 mhz, and zero wait states at 25 mhz and below. this reduces overall system cost by enabling the use of commonly available memory speeds and taking advantage of drams lower cost per bit over sram. am186ed/edlv microcontroller pins dram pin a1 ma0 a3 ma1 a5 ma2 a7 ma3 a9 ma4 a11 ma5 a13 ma6 a15 ma7 a17 ma8 ras 0ras (bank 0) ras 1ras (bank 1) ucas ucas (ad15Cad8 byte) lcas lcas (ad7Cad0 byte) rd oe wr we space auxcon field value bus width comments ucs usiz 0 16 bits dependent on boot option 1 1 8 bits lcs lsiz 0 16 bits default 1 8 bits i/o iosiz 0 16 bits default 1 8 bits other msiz 0 16 bits default 1 8 bits
38 am186ed/edlv microcontrollers preliminary d ra f t peripheral control block the integrated peripherals of the am186ed/edlv mi- crocontrollers are controlled by 16-bit read/write regis- ters. the peripheral registers are contained within an internal 256-byte peripheral control block (pcb). the registers are physically located in the peripheral de- vices they control, but they are addressed as a single 256-byte block. table 8 shows a map of these regis- ters. reading and writing the pcb code written for the am186ed/edlv microcontrollers should perform all writes to the pcb registers as byte writes. these writes transfer 16 bits of data to the pcb register even if an 8-bit register is named in the instruc- tion. for example, out dx , al results in the value of ax being written to the port address in dx . reads to the pcb should be done as word reads. code written in this manner runs correctly on the am186ed/edlv mi- crocontrollers with the pcb overlayed on either 8- or 16-bit address spaces. unaligned reads and writes to the pcb result in unpre- dictable behavior. for a complete description of all the registers in the pcb, see the am186ed/edlv microcontrollers users manual , order# 21335a.
am186ed/edlv microcontrollers 39 preliminary d ra f t table 8. peripheral control block register map all unused addresses are reserved and should not be accessed. notes: 1. the register has been modified from the am186es/ am188es microcontrollers. 2. the previous memory partition register (mdram) has been removed and its functionality replaced with the cas -before-ras refresh mode. register name offset processor control registers: peripheral control block relocation register feh reset configuration register f6h processor release level register 1 f4h auxiliary configuration register 1 f2h system configuration register 1 f0h watchdog timer control register e6h enable rcu register 1 e4h clock prescaler register 1 e2h ( see note 2 .) dma registers: dma 1 control register dah dma 1 transfer count register d8h dma 1 destination address high register d6h dma 1 destination address low register d4h dma 1 source address high register d2h dma 1 source address low register d0h dma 0 control register cah dma 0 transfer count register c8h dma 0 destination address high register c6h dma 0 destination address low register c4h dma 0 source address high register c2h dma 0 source address low register c0h chip-select registers: pcs and mcs auxiliary register a8h midrange memory chip-select register a6h peripheral chip-select register a4h low memory chip-select register 1 a2h upper memory chip-select register 1 a0h serial port 0 registers: serial port 0 baud rate divisor register 88h serial port 0 receive register 86h serial port 0 transmit register 84h serial port 0 status register 82h serial port 0 control register 80h pio registers: pio data 1 register 7ah pio direction 1 register 78h pio mode 1 register 76h pio data 0 register 74h pio direction 0 register 72h pio mode 0 register 70h timer registers: timer 2 mode/control register 66h timer 2 max count compare a register 62h timer 2 count register 60h timer 1 mode/control register 5eh timer 1 max count compare b register 5ch timer 1 max count compare a register 5ah timer 1 count register 58h timer 0 mode/control register 56h timer 0 max count compare b register 54h timer 0 max count compare a register 52h timer 0 count register 50h interrupt registers: serial port 0 interrupt control register 44h serial port 1 interrupt control register 42h int4 interrupt control register 40h int3 control register 3eh int2 control register 3ch int1 control register 3ah int0 control register 38h dma1/int6 interrupt control register 36h dma0/int5 interrupt control register 34h timer interrupt control register 32h interrupt status register 30h interrupt request register 2eh interrupt in-service register 2ch interrupt priority mask register 2ah interrupt mask register 28h interrupt poll status register 26h interrupt poll register 24h end-of-interrupt register 22h interrupt vector register 20h serial port 1 registers: serial port 1 baud rate divisor register 18h serial port 1 receive register 16h serial port 1 transmit register 14h serial port 1 status register 12h serial port 1 control register 10h register name offset
40 am186ed/edlv microcontrollers preliminary d ra f t clock and power management the clock and power management unit of the am186ed/edlv microcontrollers includes a phase- locked loop (pll) and a second programmable system clock output (clkoutb). phase-locked loop in a traditional 80c186/188 microcontroller design, the crystal frequency is twice that of the desired internal clock. because of the pll on the am186ed/edlv mi- crocontrollers, the internal clock generated by the am186ed/edlv microcontrollers (clkouta) is the same frequency as the crystal. the pll takes the crys- tal inputs (x1 and x2) and generates a 45C55% (worst case) duty cycle intermediate system clock of the same frequency. this removes the need for an external 2x oscillator, reducing system cost. the pll is reset dur- ing power-on reset by an on-chip power-on reset (por) circuit. crystal-driven clock source the internal oscillator circuit of the am186ed/edlv microcontrollers is designed to function with a parallel resonant fundamental or third overtone crystal. be- cause of the pll, the crystal frequency should be equal to the processor frequency. do not replace a crystal with an lc or rc equivalent. the x1 and x2 signals are connected to an internal in- verting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift (figure 8). in such a positive feedback circuit, the inverting amplifier has an output signal (x2) 180 de- grees out of phase of the input signal (x1). the external feedback network provides an additional 180-degree phase shift. in an ideal system, the input to x1 will have 360 or zero degrees of phase shift. the ex- ternal feedback network is designed to be as close to ideal as possible. if the feedback network is not provid- ing necessary phase shift, negative feedback dampens the output of the amplifier and negatively affects the op- eration of the clock generator. values for the loading on x1 and x2 must be chosen to provide the necessary phase shift and crystal operation. selecting a crystal when selecting a crystal, the load capacitance should always be specified (c l ). this value can cause vari- ance in the oscillation frequency from the desired spec- ified value (resonance). the load capacitance and the loading of the feedback network have the following re- lationship: where c s is the stray capacitance of the circuit. placing the crystal and c l in series across the inverting ampli- fier and tuning these values (c 1 , c 2 ) allows the crystal to oscillate at resonance. this relationship is true for both fundamental and third-overtone operation. finally, there is a relationship between c 1 and c 2 . to enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (x2). equal values of these loads tend to balance the poles of the inverting amplifier. the characteristics of the inverting amplifier set limits on the following parameters for crystals: esr (equivalent series resistance) ......60 w max drive level ..............................................1 mw max the recommended range of values for c 1 and c 2 are as follows: c 1 ..................................................................15 pf 20% c 2 ..................................................................22 pf 20% the specific values for c 1 and c 2 must be determined by the designer and are dependent on the characteris- tics of the chosen crystal and board design. figure 8. am186ed/edlv microcontrollers oscillator configurations (c 1 c 2 ) (c 1 + c 2 ) c l = + c s crystal am186ed/edlv 200 pf note 1 note 1 : use for third overtone mode xtal frequency l1 value (max) 20 mhz 12 m h 20% 25 mhz 8.2 m h 20% 33 mhz 4.7 m h 20% 40 mhz 3.0 m h 20% x1 x2 b. crystal configuration a. inverting amplifier configuration c 1 c 2 crystal c 1 c 2 microcontrollers
am186ed/edlv microcontrollers 41 preliminary d ra f t external source clock alternately, the internal oscillator can be driven from an external clock source. this source should be con- nected to the input of the inverting amplifier (x1), with the output (x2) not connected. system clocks the base system clock of amds original 80c186 and 80c188 microcontrollers is renamed clkouta and the additional output is called clkoutb. clkouta and clkoutb operate at either the processor fre- quency or the pll frequency. the output drivers for both clocks are individually programmable for disable. figure 9 shows the organization of the clocks. the second clock output (clkoutb) allows one clock to run at the pll frequency and the other clock to run at the power-save frequency. individual drive enable bits allow selective enabling of just one or both of these clock outputs. power-save operation the power-save mode of the am186ed/edlv micro- controllers reduces power consumption and heat dissi- pation, thereby extending battery life in portable systems. in power-save mode, operation of the cpu and internal peripherals continues at a slower clock fre- quency. when an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clocks next rising edge of t 3 . note: power-save operation requires that clock-de- pendent devices be reprogrammed for clock frequency changes. software drivers must be aware of clock fre- quency. the power-save divisor should not be set to operate the processor core below 100 khz. initialization and processor reset processor initialization or startup is accomplished by driving the res input pin low. res must be held low for 1 ms during power-up to ensure proper device ini- tialization. res forces the am186ed/edlv microcon- trollers to terminate all execution and local bus activity. no instruction or bus activity occurs as long as res is active. after res becomes inactive and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location ffff0h, with ucs asserted with three wait states. res also sets some registers to predefined values and resets the watchdog timer. reset configuration register when the res input is asserted low, the contents of the address/data bus (ad15Cad0) are written into the reset configuration register. the system can place con- figuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. the pro- cessor does not drive the address/data bus during re- set. for example, the reset configuration register could be used to provide the software with the position of a con- figuration switch in the system. using weak external pullup and pulldown resistors on the address and data bus, the system can provide the microcontroller with a value corresponding to the position of the jumper dur- ing a reset. figure 9. clock organization pll x1, x2 /2 clkdiv2 processor clock psen cad caf cbf cbd clkoutb clkouta mux mux mux mux time delay 6 ns power-save divisor /1 to /128 note: for frequencies under 16 mhz, use pll bypass.
42 am186ed/edlv microcontrollers preliminary d ra f t chip-select unit the am186ed/edlv microcontrollers contain logic that provides programmable chip-select generation for both memories and peripherals. the logic can be pro- grammed to provide ready and wait-state generation and latched address bits a1 and a2. the chip-select lines are active for all memory and i/o cycles in their programmed areas, whether they are generated by the cpu or by the integrated dma unit. the am186ed/edlv microcontrollers provide six chip- select outputs for use with memory devices and six more for use with peripherals in either memory space or i/o space. the six memory chip selects can be used to address three memory ranges. each peripheral chip select addresses a 256-byte block that is offset from a programmable base address. a write to a chip select register will enable the corresponding chip select logic even if the actual pin has another function (e.g., pio). chip-select timing the timing for the ucs and lcs outputs is modified from the original 80c186 microcontroller. these out- puts now assert in conjunction with the nonmultiplexed address bus for normal memory timing. to allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced. ready and wait-state programming the am186ed/edlv microcontrollers can be pro- grammed to sense a ready signal for each of the peripheral or memory chip-select lines. the ready sig- nal can be either the ardy or srdy signal. each chip- select control register (umcs, lmcs, mmcs, pacs, and mpcs) contains a single-bit field that determines whether the external ready signal is required or ignored. the number of wait states to be inserted for each ac- cess to a peripheral or memory region is programma- ble. the chip-select control registers for ucs , lcs , mcs 3Cmcs 0, pcs 6, and pcs 5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. pcs 3Cpcs 0 use three bits to pro- vide additional values of 5, 7, 9, and 15 wait states. when external ready is required, internally pro- grammed wait states will always complete before ex- ternal ready can terminate or extend a bus cycle. for example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. if external ready is as- serted at that time, the access completes after six cy- cles (four cycles plus two wait states). if external ready is not asserted during the first wait cycle, the access is extended until ready is asserted, and one more wait state occurs followed by t 4 . the ardy signal on the am186ed/edlv microcon- trollers is a true asynchronous ready signal. the ardy pin accepts a rising edge that is asynchronous to clk- outa and is active high. if the falling edge of ardy is not synchronized to clkouta as specified, an addi- tional clock period may be added. chip-select overlap although programming the various chip selects on the am186ed/edlv microcontrollers so that multiple chip select signals are asserted for the same physical ad- dress is not recommended, it may be unavoidable in some systems. in such systems, the chip selects whose assertions overlap must have the same config- uration for ready (external ready required or not re- quired) and the number of wait states to be inserted into the cycle by the processor. the one exception to this is pcs overlapping dram. the peripheral control block (pcb) is accessed using internal signals. these internal signals function as chip selects configured with zero wait states and no external ready. therefore, the pcb can be programmed to ad- dresses that overlap external chip-select signals only if those external chip selects are programmed to zero wait states with no external ready required. when overlapping an additional chip select with either the lcs or ucs chip selects, it must be noted that set- ting the disable address (da) bit in the lmcs or umcs register disables the address from being driven on the ad bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. the mcs and pcs chip-select pins can be configured as either chip selects (normal function) or as pio inputs or outputs. it should be noted, however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip se- lects or pios. this means that if these chip selects are enabled (by a write to the mmcs and mpcs for the mcs chip selects, or by a write to the pacs and mpcs registers for the pcs chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. although the pcs 4 signal is not available on an exter- nal pin, the ready and wait state logic for this signal still exists internal to the part. for this reason, the pcs 4 ad- dress space must follow the rules for overlapping chip selects. the ready and wait-state logic for pcs 6C pcs 5 is disabled when these signals are configured as address bits a2Ca1. failure to configure overlapping chip selects with the same ready and wait state requirements may cause
am186ed/edlv microcontrollers 43 preliminary d ra f t the processor to hang with the appearance of waiting for a ready signal. this behavior may occur even in a system in which ready is always asserted (ardy or srdy tied high). configuring pcs in i/o space with lcs or any other chip select configured for memory address 0 is not con- sidered overlapping of the chip selects. overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. the pcs can overlap dram blocks with different wait states and without external or internal bus contention. the ras will assert along with the appropriate pcs . the ucas and lcas will not assert, preventing the dram from writing erroneously or driving the data bus during a read. the pcs must have the same or higher number of wait states than the dram. the pcs bus width will be determined by the lsiz or usiz bus widths. this will make a 1785-byte block of the dram inaccessible. in its place, the peripherals associated with the pcs can be accessed. this is especially use- ful when the entire memory space is used with two banks of dram or a bank of dram and a 512k flash. upper memory chip select the am186ed/edlv microcontrollers provide a ucs chip select for the top of memory. on reset the am186ed/edlv microcontrollers begin fetching and executing instructions at memory location ffff0h. therefore, upper memory is usually used as instruction memory. to facilitate this usage, ucs defaults to active on reset, with a default memory range of 64 kbytes from f0000h to fffffh, with external ready required and three wait states automatically inserted. the ucs memory range always ends at fffffh. the ucs lower boundary is programmable. the bus width associated with ucs is determined on reset by the s 2/btsel. if s 2/btsel is pulled high or left floating, an internal pullup sets the boot mode op- tion to 16-bit. if s 2/btsel is pulled resistively low dur- ing reset, the boot mode option is for 8-bit. the status of the s 2/btsel pin is latched on the rising edge of re- set. if 8-bit mode is selected, the width of the memory region associated with ucs can be changed in the auxcon register. if ucs boots as a 16-bit space, it is not re-configurable to 8-bit. this allows for cheaper 8- bit-wide memory to be used for booting the am186ed/ edlv microcontrollers, while speed-critical code and data can be executed from 16-bit-wide lower memory. eight-bit or 16-bit-wide peripherals can be used in the memory area between lcs and ucs or in the i/o space. the entire memory map can be set to 16-bit or 8-bit or mixed between 8-bit and 16-bit based on the usiz, lsiz, msiz, and iosiz bits in the auxcon reg- ister. low memory chip select the am186ed/edlv microcontrollers provide an lcs chip select for lower memory. the auxcon register can be used to configure lcs for 8-bit or 16-bit ac- cesses. since the interrupt vector table is located at the bottom of memory starting at 00000h, the lcs pin is usually used to control data memory. the lcs pin is not active on reset. the lcs signal is multiplexed with the ras 0 signal when the dram mode is enabled in the lmcs register. midrange memory chip selects the am186ed/edlv microcontrollers provide four chip selects, mcs 3Cmcs 0, for use in a user-locatable memory block. with some exceptions, the base ad- dress of the memory block can be located anywhere within the 1-mbyte memory address space. the areas associated with the ucs and lcs chip selects are ex- cluded. if they are mapped to memory, the address range of the peripheral chip selects, pcs 6, pcs 5, and pcs 3Cpcs 0, are also excluded. the mcs address range can overlap the pcs address range if the pcs chip selects are mapped to i/o space. mcs 0 can be configured to be asserted for the entire mcs range. when configured in this mode, the mcs 3C mc s 1 pins can be used as pios or dram control sig- nals. the auxcon register can be used to configure mcs for 8-bit or 16-bit accesses. the bus width of the mcs range is determined by the width of the non-ucs /non- lcs memory range. unlike the ucs and lcs chip selects, the mcs outputs assert with the same timing as the multiplexed ad ad- dress bus. activating either bank of dram will change the mcs 1 and mcs 2 functionality to ucas and lcas . activating the upper dram bank will change the mcs 3 function- ality to ras 1. it is recommended that when either bank of dram is activated, either mcs 0 be configured to as- sert for the entire mcs range or that mcs space be un- used. if the lower bank of dram is activated, but not the upper bank of dram, mcs 3 can still be used as a chip select or pio. the mcs 2 and mcs 1 portion of the middle chip select address space will not have a chip select signal asserted, but the wait states will still be valid. peripheral chip selects the am186ed/edlv microcontrollers provide six chip selects, pcs 6Cpcs 5 and pcs 3Cpcs 0, for use within a user-configured memory or i/o block. pcs 4 is not available on the am186ed/edlv microcontrollers. the base address of the memory block can be located any- where within the 1-mbyte memory address space, ex- clusive of the areas associated with the ucs , lcs , and
44 am186ed/edlv microcontrollers preliminary d ra f t mcs chip selects, or they can be configured to access the 64-kbyte i/o space. the pcs pins are not active on reset. pcs 6Cpcs 5 can be programmed for zero to three wait states. pcs 3C pcs 0 can be programmed for four additional wait-state values: 5, 7, 9, and 15. the auxcon register can be used to configure pcs for 8-bit or 16-bit accesses. the bus width of the pcs range is determined by the width of the non-ucs /non- lcs memory range or by the width of the i/o area. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186/188 microcon- trollers. the pcs allows for overlap in memory space with the dram (ras 0, ras 1) space. overlap of the pcs with lcs , mcs , or ucs in a non-dram mode is not recom- mended. if overlap of the pcs with mcs , lcs , or ucs occurs, the same number of wait states and external ready must be used. if overlap of pcs with dram space occurs, the dram controller will assert ras and stop the cas signal from asserting. this will not modify the contents of the dram and the access will continue as a normal pcs access. when overlapping the pcs with dram, the number of wait states can be different for pcs space. pcs wait states must be greater than or equal to dram wait states. the ready and wait states will be determined by the pcs programming in the mpcs and pacs registers. pcs space should not contain the address fffffh, which is the address used for a refresh cycle. the ad15Cad0 bus will drive ffffh during a refresh cycle for the address portion of cycle. refresh control unit the refresh control unit (rcu) automatically generates refresh bus cycles when enabled. after a programma- ble period of time, the rcu generates a cas -before- ras refresh bus cycle. the rcu should not be en- abled if at least one bank of dram is not enabled. all refreshes will be 7 clocks, no matter how the dram wait states are programmed. during a refresh cycle, the a19Ca0 bus is undefined; the ad15Cad0 bus is driven with all 1s (ffffh). the pcs and mcs chip se- lects are decoded by the processor using a 20-bit ver- sion of the ad bus. the highest four bits of this internal bus are not available externally; however, internally these bits are set to all 1s during a refresh cycle, result- ing in the 20-bit address fffffh. for this reason, the mcs and pcs chip selects should not contain the ad- dress fffffh while dram is enabled. interrupt control unit the am186ed/edlv microcontrollers can receive in- terrupt requests from a variety of sources, both internal and external. the internal interrupt controller arranges these requests by priority and presents them one at a time to the cpu. there are up to eight external interrupt sources on the am186ed/edlv microcontrollersseven maskable interrupt pins and one nonmaskable interrupt (nmi) pin. in addition, there are eight internal interrupt sources (three timers, two dma channels, two asyn- chronous serial ports, and the watchdog timer nmi) that are not connected to external pins. int5 and int6 are multiplexed with drq0 and drq1. these two in- terrupts are available if the associated dma is not en- abled or is being used with internal synchronization. the am186ed/edlv microcontrollers provide up to six interrupt sources not present on the 80c186 and 80c188 microcontrollers. there are up to three addi- tional external interrupt pinsint4, int5, and int6. these pins operate much like the int3Cint0 interrupt pins on the 80c186 and 80c188 microcontrollers. there are also two internal interrupts from the serial ports and the watchdog timer can generate interrupts. int5 and int6 are multiplexed with the dma request signals, drq0 and drq1. if a dma channel is not en- abled, or if it is not using external synchronization, then the associated pin can be used as an external interrupt. int5 and int6 can also be used in conjunction with the dma terminal count interrupts. the seven maskable interrupt request pins can be used as direct interrupt requests. int4Cint0 can be ei- ther edge-triggered or level-triggered. int6 and int5 are edge-triggered only. in addition, int0 and int1 can be configured in cascade mode for use with an external 82c59a-compatible interrupt controller. when int0 is configured in cascade mode, the int2 pin is automati- cally configured in its inta 0 function. when int1 is configured in cascade mode, the int3 pin is automati- cally configured in its inta 1 function. an external inter- rupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. int6Cint4 are not available in slave mode. interrupts are automatically disabled when an interrupt is taken. interrupt-service routines (isrs) may re-enable interrupts by setting the if flag. this allows interrupts of greater or equal priority to interrupt the currently executing isr. interrupts from the same source are disabled as long as the corresponding bit in the interrupt in-service register is set. int1 and int0 provide a special bit to enable special fully nested mode. when configured in special fully nested mode, the interrupt source may generate a new interrupt regardless of the setting of the in-service bit.
am186ed/edlv microcontrollers 45 preliminary d ra f t timer control unit there are three 16-bit programmable timers and a watchdog timer on the am186ed/edlv microcontrol- lers. timer 0 and timer 1 are connected to four external pins (each one has an input and an output). these two tim- ers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle wave- forms. when pulse width demodulation is enabled, timer 0 and timer 1 are used to measure the width of the high and low pulses on the pwd pin. (see the pulse width demodulation section on page 45.) timer 2 is not connected to any external pins. it can be used for real-time coding and time-delay applications. it can also be used as a prescaler to timers 0 and 1 or to synchronize dma transfers. the programmable timers are controlled by eleven 16- bit registers in the peripheral control block. a timers timer-count register contains the current value of that timer. the timer-count register can be read or written with a value at any time, whether the timer is running or not. the microcontroller increments the value of the timer-count register each time a timer event occurs. each timer also has a maximum-count register that de- fines the maximum value the timer can reach. when the timer reaches the maximum value, it resets to 0 during the same clock cycle. the value in the maxi- mum-count register is never stored in the timer-count register. also, timers 0 and 1 have a secondary maxi- mum-count register. using both the primary and sec- ondary maximum-count registers lets the timer alternate between two maximum values. if the timer is programmed to use only the primary max- imum-count register, the timer output pin switches low for one clock cycle after the maximum value is reached. if the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. the duty cycle of the waveform depends on the values in the maximum- count registers. each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter of the internal clock frequency. a timer can be clocked exter- nally at this same frequency; however, because of in- ternal synchronization and pipelining of the timer circuitry, the timer output can take up to six clock cycles to respond to the clock or gate input. watchdog timer the am186ed/edlv microcontrollers provide a true watchdog timer function. the watchdog timer (wdt) can be used to regain control of the system when soft- ware fails to respond as expected. the wdt is active after reset. it can only be modified a single time by a keyed sequence of writes to the watchdog timer control register (wdtcon) following reset. this single write can either disable the timer or modify the timeout pe- riod and the action taken upon timeout. a keyed se- quence is also required to reset the current wdt count. this behavior ensures that randomly executing code will not prevent a wdt event from occurring. the wdt supports up to a 1.67-second timeout period in a 40-mhz system. after reset, the wdt is enabled and the timeout period is set to its maximum value. the wdt can be configured to cause either an nmi in- terrupt or a system reset upon timeout. if the wdt is configured for nmi, the nmiflag in the wdtcon reg- ister is set when the nmi is generated. the nmi inter- rupt service routine (isr) should examine this flag to determine if the interrupt was generated by the wdt or by an external source. if the nmiflag is set, the isr should clear the flag by writing the correct keyed se- quence to the wdtcon register. if the nmiflag is set when a second wdt timeout occurs, a wdt system reset is generated rather than a second nmi event. when the processor takes a wdt reset, either due to a single wdt event with the wdt configured to gener- ate resets or due to a wdt event with the nmiflag set, the rstflag in the wdtcon register is set. this allows system initialization code to differentiate be- tween a hardware reset and a wdt reset and take ap- propriate action. the rstflag is cleared when the wdtcon register is read or written. the processor does not resample external pins during a wdt reset. this means that the clocking, the reset configuration register, and any other features that are user-select- able during reset do not change when a wdt system reset occurs. all other activities are identical to those of a normal system reset. note: the watchdog timer (wdt) is active after re- set. pulse width demodulation for many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its high and low phases. the am186ed/edlv microcon- trollers provide a pulse-width demodulation (pwd) op- tion to fulfill this need. the pwd bit in the system configuration register (syscon) enables the pwd option. analog-to-digital conversion is not supported. in pwd mode, tmrin0, tmrin1, int2, and int4 are configured internal to the microcontroller to support the detection of rising and falling edges on the pwd input pin (int2/inta 0/pwd) and to enable either timer 0 when the signal is high or timer 1 when the signal is low. the int4, tmrin0, and tmrin1 pins are not used in pwd mode and so are available for use as pios.
46 am186ed/edlv microcontrollers preliminary d ra f t the following diagram shows the behavior of a system for a typical waveform. the interrupt service routine (isr) for the int2 and int4 interrupts should examine the current count of the associated timer, timer 1 for int2, and timer 0 for int4, in order to determine the pulse width. the isr should then reset the timer count register in preparation for the next pulse. since the timers count at one quarter of the processor clock rate, this determines the maximum resolution that can be obtained. further, in applications where the pulse width may be short, it may be necessary to poll the int2 and int4 request bits in the interrupt request register in order to avoid the overhead involved in tak- ing and returning from an interrupt. overflow condi- tions, where the pulse width is greater than the maximum count of the timer, can be detected by moni- toring the maximum count (mc) bit in the associated timer or by setting the int bit to enable timer interrupt requests. direct memory access direct memory access (dma) permits transfer of data between memory and peripherals without cpu involve- ment. the dma unit shown in figure 10, provides two high-speed dma channels. data transfers can occur between memory and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory to memory or i/o to i/o). table 9 shows maximum dma transfer rates. the dma channels can be directly connected to the asynchronous serial ports. dma and serial port transfer is accomplished by programming the dma controller to perform transfers between a data source in memory or i/o space and a serial port transmit or receive register. the two dma channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode. either bytes or words can be transferred to or from even or odd addresses. however, word dma transfers to or from memory configured for 8-bit accesses are not supported. only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. each channel accepts a dma request from one of four sources: the channel request pin (drq 1Cdrq0), timer 2, a serial port, or the system software. the channels can be programmed with different priorities in the event of a simultaneous dma request or if there is a need to interrupt transfers on the other channel. dma operation each channel has six registers in the peripheral control block that define specific channel operations. the dma registers consist of a 20-bit source address (two regis- ters), a 20-bit destination address (two registers), a 16- bit transfer count register, and a 16-bit control register. the dma transfer count register (dtc) specifies the number of dma transfers to be performed. up to 64k of byte or word transfers can be performed with auto- matic termination. the dma control registers define the channel operation. all registers can be modified dur- ing any dma activity. any changes made to the dma registers are reflected immediately in dma operation. table 9. am186ed/edlv microcontrollers maximum dma transfer rates int2 int4 int2 ints generated tmr1 enabled tmr0 enabled type of synchronization selected maximum dma transfer rate (mbytes) 40 mhz 33 mhz 25 mhz 20 mhz unsynchronized 10 8.25 6.25 5 source synchronized 10 8.25 6.25 5 destination synchronized (cpu needs bus) 6.6 5.5 4.16 3.3 destination synch (cpu does not need bus) 86.65 4
am186ed/edlv microcontrollers 47 preliminary d ra f t figure 10. dma unit block diagram dma channel control registers each dma control register determines the mode of op- eration for the particular dma channel. the dma con- trol registers specify the following: n the mode of synchronization n whether bytes or words are transferred n whether an interrupt is generated after the last transfer n whether the drq pins are configured as int pins n whether dma activity ceases after a programmed number of dma cycles n the relative priority of the dma channel with re- spect to the other dma channel n whether the source address is incremented, decre- mented, or maintained constant after each transfer n whether the source address addresses memory or i/o space n whether the destination address is incremented, decremented, or maintained constant after trans- fers n whether the destination address addresses mem- ory or i/o space dma priority the dma channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have dma requests pending. dma cycles always have priority over internal cpu cycles except between locked memory accesses or word accesses to odd memory locations. however, an external bus hold takes priority over an internal dma cycle. because an interrupt request cannot suspend a dma operation and the cpu cannot access memory during a dma cycle, interrupt latency time suffers during se- quences of continuous dma cycles. an nmi request, however, causes all internal dma activity to halt. this allows the cpu to respond quickly to the nmi request. asynchronous serial ports the am186ed/edlv microcontrollers provide two in- dependent asynchronous serial ports. these ports pro- vide full-duplex, bidirectional data transfer using several industry-standard communications protocols. the serial ports can be used as sources or destinations of dma transfers. 20-bit adder/subtractor dma control logic request selection logic adder control logic 20 20 channel control register 1 channel control register 0 16 drq1/serial port drq0/serial port timer request interrupt request transfer counter ch. 1 destination address ch. 1 destination address ch. 0 transfer counter ch. 0 source address ch. 1 source address ch. 0 internal address/data bus
48 am186ed/edlv microcontrollers preliminary d ra f t the asynchronous serial ports support the following features: n full-duplex operation n direct memory access (dma) from the serial ports n 7-bit, 8-bit, or 9-bit data transfers n odd, even, or no parity n one stop bit n long or short break character recognition n error detection parity errors framing errors overrun errors break character recognition n hardware handshaking with the following select- able control signals: clear-to-send (cts ) enable-receiver-request (enrx ) ready-to-send (rts ) ready-to-receive (rtr ) n dma to and from the serial ports n separate maskable interrupts for each port n multidrop protocol (9-bit) support n independent baud rate generators n maximum baud rate of 1/16th of the cpu clock n double-buffered transmit and receive n programmable interrupt generation for transmit, re- ceive, and/or error detection dma transfers through the serial port the dma channels can be directly connected to the asynchronous serial ports. dma and serial port transfer is accomplished by programming the dma controller to perform transfers between a memory or i/o space and a serial port transmit or receive register. the two dma channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode. see the dma control register descriptions in the am186ed/ edlv microcontrollers users manual , order# 21335a for more information. programmable i/o (pio) pins there are 32 pins on the am186ed/edlv microcon- trollers that are available as user-programmable i/o signals. table 2 on page 29 and table 3 on page 29 list the pio pins. each of these pins can be used as a user- programmable input or output signal if the normal shared function is not needed. if a pin is enabled to function as a pio signal, the pre- assigned signal function is disabled and does not affect the level on the pin. a pio signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. after power-on reset, the pio pins default to various configurations. the column titled power-on reset sta- tus in table 2 on page 29 and table 3 on page 29 lists the defaults for the pios. the system initialization code must reconfigure the pios as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. note that emulators use a19, a18, a17, s6, and uzi . in environments where an emulator is needed, these pins must be configured for normal functionnot as pios. if the ad15Cad0 bus override is enabled on power-on reset, then s6/clkdiv 2 and uzi revert to normal oper- ation instead of pio input with pullup. if bhe /aden is held low during power-on reset, the ad15Cad0 bus override is enabled. when the pcs or mcs are used as pio inputs (only) and the bus is arbitrated, an internal pullup of ~10 kohms is activated, even if the pullup option for the pio is not selected.
am186ed/edlv microcontrollers 49 preliminary d ra f t absolute maximum ratings storage temperature am186ed........................................ C65 c to +125 c am186edlv.................................... C65 c to +125 c voltage on any pin with respect to ground am186ed................................... C0.5 v to v cc +0.5 v am186edlv............................... C0.5 v to v cc +0.5 v note: stresses above those listed under absolute maximum ratings may cause permanent device fail- ure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges am186ed microcontroller commercial (t c ) .................................0 c to +100 c industrial* (t a )...................................C40 c to +85 c supply voltage (v cc ) .................................5 v 10% am186edlv microcontroller commercial (t a ) ................................... 0 c to +70 c v cc up to 25 mhz................................. 3.3 v 0.3 v where: t c = case temperature t a = ambient temperature *industrial versions of am186ed microcontrollers are available in 20 and 25 mhz operating frequencies only. dc characteristics over commercial and industrial operating ranges notes: a the lcs /once 0/ras 0 and ucs /once 1 pins have weak internal pullup resistors. loading the lcs /once 0/ras 0 and ucs /once 1 pins in excess of i oh = C200 m a during reset can cause the device to go into once mode. b current is measured with the device in reset with x1 and x2 driven and all other non-power pins open but held high or low. c testing is performed with the pins floating, either during hold or by invoking the once mode. symbol parameter description test conditions preliminary unit min max v il input low voltage (except x1) C0.5 0.2v cc C0.3 v v il 1 clock input low voltage (x1) C0.5 0.8 v v ih input high voltage (except res and x1) 2.0 v cc +0.5 v v ih 1 input high voltage (res )2.4v cc +0.5 v v ih 2 clock input high voltage (x1) v cc C0.8 v cc +0.5 v v ol output low voltage am186ed i ol = 2.5 ma (s 2Cs 0) i ol = 2.0 ma (others) 0.45 v am186edlv i ol = 1.5 ma (s 2Cs 0) i ol = 1.0 ma (others) 0.45 v v oh output high voltage (a) am186ed i oh = C2.4 ma @ 2.4 v 2.4 v cc +0.5 v i oh = C200 m a @ v cc C0.5 v cc C0.5 v cc v am186edlv i oh = C200 m a @ v cc C0.5 v cc C0.5 v cc v i cc power supply current @ 0 cv cc = 5.5 v (b) v cc = 3.6 v (b) 5.9 4.0 ma/mhz i li input leakage current @ 0.5 mhz 0.45 v v in v cc 10 m a i lo output leakage current @ 0.5 mhz 0.45 v v out v cc (c) 10 m a v clo clock output low i clo = 4.0 ma 0.45 v v cho clock output high i cho = C500 m av cc C0.5 v
50 am186ed/edlv microcontrollers preliminary d ra f t capacitance note: capacitance limits are guaranteed by characterization. power supply current for the following typical system specification shown in figure 11, i cc has been measured at 4.0 ma per mhz of system clock. for the following typical system specification shown in figure 12, i cc has been measured at 5.9 ma per mhz of system clock. the typical system is measured while the system is executing code in a typical application with nominal voltage and maximum case temperature. actual power supply current is dependent on system design and may be greater or less than the typical i cc figure presented here. typical current in figure 11 is given by: i cc = 4.0 ma freq(mhz) typical current in figure 12 is given by: i cc = 5.9 ma freq(mhz) please note that dynamic i cc measurements are de- pendent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the out- puts. for these i cc measurements, the devices were set to the following modes: n no dc loads on the output buffers n output capacitive load set to 35 pf n ad bus set to data only n pios are disabled n timer, serial port, refresh, and dma are enabled table 10 shows the variables that are used to calculate the typical power consumption value for the am186edlv microcontroller. table 10. typical power consumption calculation for the am186edlv microcontroller figure 11. typical i cc versus frequency for am186edlv microcontroller figure 12. typical i cc versus frequency for am186ed microcontroller preliminary symbol parameter description test conditions min max unit c in input capacitance @ 1 mhz 10 pf c io output or i/o capacitance @ 1 mhz 20 pf mhz i cc volts / 1000 = p typical power in watts mhz typical i cc volts 20 4.0 3.6 0.288 25 4.0 3.6 0.360 clock frequency (mhz) i cc (ma) 25 mhz 20 mhz 0 20 40 60 80 100 120 140 10 20 30 clock frequency (mhz) i cc (ma) 33 mhz 20 mhz 40 mhz 0 40 80 120 160 200 240 280 10 20 30 40 50 25 mhz
am186ed/edlv microcontrollers 51 preliminary d ra f t thermal characteristics tqfp package the am186ed microcontroller is specified for operation with case temperature ranges from 0 c to +100 c for a commercial device. case temperature is measured at the top center of the package as shown in figure 13. the various temperatures and thermal resistances can be determined using the equations in figure 14 with information given in table 11. the total thermal resistance is q ja ; q ja is the sum of q jc , the internal thermal resistance of the assembly, and q ca , the case to ambient thermal resistance. the variable p is power in watts. power supply current (i cc) is in ma per mhz of clock frequency. figure 13. thermal resistance( c/watt) figure 14. thermal characteristics equations table 11. thermal characteristics ( c/watt) q ja q ca q jc q ja = q jc + q ca t c package/board airflow (linear feet per minute) q ja q jc q ca pqfp/2-layer 0 fpm 45 7 38 200 fpm 39 7 32 400 fpm 35 7 28 600 fpm 33 7 26 tqfp/2-layer 0 fpm 56 10 46 200 fpm 461036 400 fpm 401030 600 fpm 381028 pqfp/4-layer to 6-layer 0 fpm 23518 200 fpm 21 5 16 400 fpm 19 5 14 600 fpm 17 5 12 tqfp/4-layer to 6-layer 0 fpm 30624 200 fpm 28 6 22 400 fpm 26 6 20 600 fpm 24 6 18 q ja = q jc + q ca p=i cc freq (mhz) v cc t j =t c +( p q jc ) t j =t a + ( p q ja ) t c =t j C( p q jc ) t c =t a +( p q ca ) t a =t j C( p q ja ) t a =t c C( p q ca )
52 am186ed/edlv microcontrollers preliminary d ra f t typical ambient temperatures the typical ambient temperature specifications are based on the following assumptions and calculations: the commercial operating range of the am186ed microcontroller is a case temperature t c of 0 to 100 degrees centigrade. t c is measured at the top center of the package. an increase in the ambient temperature causes a proportional increase in t c . microcontrollers up to 40 mhz are specified as 5.0 v plus or minus 10%. therefore, 5.0 v is used for calculating typical power consumption up to 40 mhz. typical power supply current (i cc ) in normal usage is estimated at 5.9 ma per mhz of microcontroller clock rate. typical power consumption (watts) = (5.9 ma/mhz) times microcontroller clock rate times v cc divided by 1000. table 12 shows the variables that are used to calculate the typical power consumption value for each version of the am186ed microcontroller. table 12. typical power consumption calculation thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. a safe operating range for the device can be calculated using the formulas from figure 14 and the variables in ta b l e 11 . by using the maximum case rating t c , the typical power consumption value from table 12, and q jc from table 11, the junction temperature t j can be calculated by using the following formula from figure 14. t j = t c + (p q jc ) table 13 shows t j values for the various versions of the am186ed microcontroller. the column titled speed/pkg/board in table 13 indicates the clock speed in mhz, the type of package (p for pqfp and t for tqfp), and the type of board (2 for 2-layer and 4-6 for 4-layer to 6-layer). table 13. junction temperature calculation by using t j from table 13, the typical power consumption value from table 12, and a q ja value from table 11, the typical ambient temperature t a can be calculated using the following formula from figure 14: t a = t j C (p q ja ) for example, t a for a 40-mhz pqfp design with a 2- layer board and 0 fpm airflow is calculated as follows: t a = 108.3 C (1.2 45) t a = 55.2 in this calculation, t j comes from table 13, p comes from table 12, and q ja comes from table 11. see table 14. t a for a 33-mhz tqfp design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: t a = 105.8 C (1.0 28) t a = 78.6 see table 17 for the result of this calculation. table 14 through table 17 and figure 15 through figure 18 show t a based on the preceding assumptions and calculations for a range of q ja values with airflow from 0 linear feet per minute to 600 linear feet per minute. p = mhz i cc v cc /1000 typical power (p) in watts mhz typical i cc volts 40 5.9 5.0 1.2 33 5.9 5.0 1.0 25 5.9 5.0 0.7 20 5.9 5.0 0.6 speed/ pkg/ board t j (c) t j = t c + (p q jc ) t c p q jc 40/p2 108.3 100 1.2 7 40/t2 111.8 100 1.2 10 40/p4-6 105.9 100 1.2 5 40/t4-6 107.1 100 1.2 6 33/p2 106.8 100 1.0 7 33/t2 109.7 100 1.0 10 33/p4-6 104.9 100 1.0 5 33/t4-6 105.8 100 1.0 6 25/p2 105.2 100 0.7 7 25/t2 107.4 100 0.7 10 25/p4-6 103.7 100 0.7 5 25/t4-6 104.4 100 0.7 6 20/p2 104.1 100 0.6 7 20/t2 105.9 100 0.6 10 20/p4-6 103.0 100 0.6 5 20/t4-6 103.5 100 0.6 6
am186ed/edlv microcontrollers 53 preliminary d ra f t table 14 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used on a 2- layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 15 graphically illustrates the typical temperatures in table 14. table 14. typical ambient temperatures (c) for pqfp with a 2-layer board figure 15. typical ambient temperatures for pqfp with a 2-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.2 55.2 62.2 67.0 69.3 33 mhz 1.0 63.0 68.8 72.7 74.7 25 mhz 0.7 72.0 76.4 79.4 80.8 20 mhz 0.6 77.6 81.1 83.5 84.7 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 40 50 60 70 80 90 l l l l v v v v u u u u n n n n
54 am186ed/edlv microcontrollers preliminary d ra f t table 15 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used on a 2- layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 16 graphically illustrates the typical temperatures in table 15. table 15. typical ambient temperatures (c) for tqfp with a 2-layer board figure 16. typical ambient temperatures for tqfp with a 2-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.2 45.7 57.5 64.6 67.0 33 mhz 1.0 55.2 65.0 70.8 72.7 25 mhz 0.7 66.1 73.5 77.9 79.4 20 mhz 0.6 72.9 78.8 82.3 83.5 airflow (linear feet per minute) l l l l v v v v u u u u n n n n 0 fpm 200 fpm 400 fpm 600 fpm l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 35 45 55 65 75 85 typical ambient temperature (degrees c)
am186ed/edlv microcontrollers 55 preliminary d ra f t table 16 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used on a 4- layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 17 graphically illustrates the typical temperatures in table 16. table 16. typical ambient te mperatures (c) for pqfp with a 4-layer to 6-layer board figure 17. typical ambient temperatures for pqfp with a 4-layer to 6-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.2 78.8 81.1 83.5 85.8 33 mhz 1.0 82.5 84.4 86.4 88.3 25 mhz 0.7 86.7 88.2 89.7 91.2 20 mhz 0.6 89.4 90.6 91.7 92.9 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 70 75 80 85 90 95 airflow (linear feet per minute) l l l l v v v v u u u u n n n n
56 am186ed/edlv microcontrollers preliminary d ra f t table 17 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used on a 4- layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 18 graphically illustrates the typical temperatures in table 17. table 17. typical am bient temperatures (c) for tqfp with a 4-layer to 6-layer board figure 18. typical ambient temperatures for tqfp with a 4-layer to 6-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.2 71.7 74.0 76.4 78.8 33 mhz 1.0 76.6 78.6 80.5 82.5 25 mhz 0.7 82.3 83.8 85.3 86.7 20 mhz 0.6 85.8 87.0 88.2 89.4 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) 65 70 75 80 85 90 l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: airflow (linear feet per minute) l l l l v v v v u u u u n n n n
am186ed/edlv microcontrollers 57 preliminary d ra f t commercial and industrial switching characteristics and waveforms in the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. these periods are referred to as time states. a typical bus cycle is composed of four consecutive time states: t 1 , t 2 , t 3 , and t 4 . wait states, which represent multiple t 3 states, are referred to as t w states. when no bus cycle is pending, an idle (t i ) state occurs. in the switching parameter descriptions, the multiplexed address is referred to as the ad address bus; the demultiplexed address is referred to as the a address bus. key to switching waveforms must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform input output invalid invalid
58 am186ed/edlv microcontrollers preliminary d ra f t alphabetical key to switching parameter symbols parameter symbol no. description t arych 49 ardy resolution transition setup time t arychl 51 ardy inactive holding time t aryhdsh (a) 95 ardy high to ds high t aryhdv (a) 89 ardy assert to data valid t arylcl 52 ardy setup time t aryldsh (a) 96 ardy low to ds high t avbl 87 a address valid to whb , wlb low t avch 14 ad address valid to clock high t avll 12 ad address valid to ale low t avrl 66 a address valid to rd low t avwl 65 a address valid to wr low t azrl 24 ad address float to rd active t ch1ch2 45 clkouta rise time t chav 68 clkouta high to a address valid t chca 104 clkouta high to cas active t chcav 101 clkouta low to column address valid t chck 38 x1 high time t chcl 44 clkouta high time t chcsv 67 clkouta high to lcs /ucs valid t chcsx 18 mcs /pcs inactive delay t chctv 22 control active delay 2 t chcv 64 command lines valid delay (after float) t chcz 63 command lines float delay t chdx 8 status hold time t chlh 9 ale active delay t chll 11 ale inactive delay t chra 106 clkouta high to ras active t chsv 3 status active delay t cicoa 69 x1 to clkouta skew t cicob 70 x1 to clkoutb skew t chrx 103 clkouta high to ras inactive t ckhl 39 x1 fall time t ckin 36 x1 period t cklh 40 x1 rise time t cl2cl1 46 clkouta fall time t clarx 50 ardy active hold time t clav 5 ad address valid delay and bhe t clax 6 address hold t claz 15 ad address float delay t clch 43 clkouta low time t clck 37 x1 low time t clcl 42 clkouta period
am186ed/edlv microcontrollers 59 preliminary d ra f t alphabetical key to switching parameter symbols (continued) parameter symbol no. description t clcsv 16 mcs /pcs active delay t clcx 105 clkouta low to cas inactive t clrx 107 clkouta low to ras inactive t cldox 30 data hold time t cldv 7 data valid delay t cldx 2 data in hold t clhav 62 hlda valid delay t clra 102 clkouta low to ras active t clrh 27 rd inactive delay t clrl 25 rd active delay t clsh 4 status inactive delay t clsry 48 srdy transition hold time t cltmv 55 timer output delay t coaob (a) 83 clkouta to clkoutb skew t csharyl (a) 88 chip select to ardy low t cvctv 20 control active delay 1 t cvctx 31 control inactive delay t cvdex 21 den inactive delay t cxcsx 17 mcs /pcs hold from command inactive t dshdir (a) 92 ds high to data invalidread t dshdiw 98 ds high to data invalidwrite t dshdx (a) 93 ds high to data bus turn-off time t dshlh 41 ds inactive to ale inactive t dsldd (a) 90 ds low to data driven t dsldv (a) 91 ds low to data valid t dvcl 1 data in setup t dvdsl (a) 97 data valid to ds low t dxdl 19 den inactive to dt/r low t hvcl 58 hold setup t invch 53 peripheral setup time t invcl 54 drq setup time t lhav 23 ale high to address valid t lhll 10 ale width t llax 13 ad address hold from ale inactive t lock 61 maximum pll lock time t plal 99 pcs active to ale inactive t rd0w 110 ras to column address delay time with 0 wait states t rd1w 111 ras to column address delay time with 1 or more wait states t resin 57 res setup time t rhav 29 rd inactive to ad address active t rhdx 59 rd high to data hold on ad bus t rhdz (a) 94 rd high to data bus turn-off time t rhlh 28 rd inactive to ale high
60 am186ed/edlv microcontrollers preliminary d ra f t alphabetical key to switching parameter symbols (continued) note: a specs 83 and 88C97 are defined but not used at this time. additionally, the following parameters are not defined nor used at this time: 56, 60, and 71C78. parameter symbol no. description t rlrh 26 rd pulse width t rp0w 108 ras inactive pulse width (0 wait states) t rp1w 109 ras inactive pulse width (1 wait state) t srycl 47 srdy transition setup time t whdex 35 wr inactive to den inactive t whdx 34 data hold after wr t whlh 33 wr inactive to ale high t wlwh 32 wr pulse width
am186ed/edlv microcontrollers 61 preliminary d ra f t numerical key to switching parameter symbols no. parameter symbol description 1 t dvcl data in setup 2 t cldx data in hold 3 t chsv status active delay 4 t clsh status inactive delay 5 t clav ad address valid delay and bhe 6 t clax address hold 7 t cldv data valid delay 8 t chdx status hold time 9 t chlh ale active delay 10 t lhll ale width 11 t chll ale inactive delay 12 t avll ad address valid to ale low 13 t llax ad address hold from ale inactive 14 t avch ad address valid to clock high 15 t claz ad address float delay 16 t clcsv mcs /pcs active delay 17 t cxcsx mcs /pcs hold from command inactive 18 t chcsx mcs /pcs inactive delay 19 t dxdl den inactive to dt/r low 20 t cvctv control active delay 1 21 t cvdex den inactive delay 22 t chctv control active delay 2 23 t lhav ale high to address valid 24 t azrl ad address float to rd active 25 t clrl rd active delay 26 t rlrh rd pulse width 27 t clrh rd inactive delay 28 t rhlh rd inactive to ale high 29 t rhav rd inactive to ad address active 30 t cldox data hold time 31 t cvctx control inactive delay 32 t wlwh wr pulse width 33 t whlh wr inactive to ale high 34 t whdx data hold after wr 35 t whdex wr inactive to den inactive 36 t ckin x1 period 37 t clck x1 low time 38 t chck x1 high time 39 t ckhl x1 fall time 40 t cklh x1 rise time 41 t dshlh ds inactive to ale inactive 42 t clcl clkouta period
62 am186ed/edlv microcontrollers preliminary d ra f t numerical key to switching parameter symbols (continued) no. parameter symbol description 43 t clch clkouta low time 44 t chcl clkouta high time 45 t ch1ch2 clkouta rise time 46 t cl2cl1 clkouta fall time 47 t srycl srdy transition setup time 48 t clsry srdy transition hold time 49 t arych ardy resolution transition setup time 50 t clarx ardy active hold time 51 t arychl ardy inactive holding time 52 t arylcl ardy setup time 53 t invch peripheral setup time 54 t invcl drq setup time 55 t cltmv timer output delay 57 t resin res setup time 58 t hvcl hold setup 59 t rhdx rd high to data hold on ad bus 61 t lock maximum pll lock time 62 t clhav hlda valid delay 63 t chcz command lines float delay 64 t chcv command lines valid delay (after float) 65 t avwl a address valid to wr low 66 t avrl a address valid to rd low 67 t chcsv clkouta high to lcs /ucs valid 68 t chav clkouta high to a address valid 69 t cicoa x1 to clkouta skew 70 t cicob x1 to clkoutb skew 83 (a) t coaob clkouta to clkoutb skew 87 t avbl a address valid to whb , wlb low 88 (a) t csharyl chip select to ardy low 89 (a) t aryhdv ardy assert to data valid 90 (a) t dsldd ds low to data driven 91 (a) t dsldv ds low to data valid 92 (a) t dshdir ds high to data invalidread 93 (a) t dshdx ds high to data bus turn-off time
am186ed/edlv microcontrollers 63 preliminary d ra f t numerical key to switching parameter symbols (continued) note: a specs 83 and 88C97 are defined but not used at this time. additionally, the following parameters are not defined nor used at this time: 56, 60, and 71C78. no. parameter symbol description 94 (a) t rhdz rd high to data bus turn-off time 95 (a) t aryhdsh ardy high to ds high 96 (a) t aryldsh ardy low to ds high 97 (a) t dvdsl data valid to ds low 98 t dshdiw ds high to data invalidwrite 99 t plal pcs active to ale inactive 101 t chcav clkouta low to column address valid 102 t clra clkouta low to ras active 103 t chrx clkouta high to ras inactive 104 t chca clkouta high to cas active 105 t clcx clkouta low to cas inactive 106 t chra clkouta high to ras active 107 t clrx clkouta low to ras inactive 108 t rp0w ras inactive pulse width (0 wait states) 109 t rp1w ras inactive pulse width (1 wait state) 110 t rd0w ras to column address delay time with 0 wait states 111 t rd1w ras to column address delay time with 1 or more wait states
64 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial and industrial operating ranges read cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 10 10 ns 2t cldx data in hold (c) 33ns general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 5t clav ad address valid delay and bhe 0 25 0 20 ns 6t clax address hold 0 25 0 20 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 25 t clax =0 20 ns 16 t clcsv mcs /pcs active delay 0 25 0 20 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 25 0 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 025020ns 21 t cvdex den inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 (b) 025020ns 23 t lhav ale high to address valid 20 15 ns 99 t plal pcs active to ale inactive 15 28 15 24 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15=85 2t clcl C15=65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 29 t rhav rd inactive to ad address active (a) t clcl C10=40 t clcl C10=30 ns 41 t dshlh ds inactive to ale active t clch C2=21 t clch C2=16 ns 59 t rhdx rd high to data hold on ad bus (c) 00ns 66 t avrl a address valid to rd low (a) t clcl + t chcl C3 t clcl + t chcl C3 ns 67 t chcsv clkouta high to lcs /ucs valid 0 25 0 20 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns
am186ed/edlv microcontrollers 65 preliminary d ra f t switching characteristics over commercial operating ranges read cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 8 5 ns 2t cldx data in hold (c) 32ns general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 5t clav ad address valid delay and bhe 0 15 0 12 ns 6t clax address hold 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 15 t clax =0 12 ns 16 t clcsv mcs /pcs active delay 0 15 0 12 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 15 0 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015012ns 21 t cvdex den inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 (b) 015012ns 23 t lhav ale high to address valid 10 7.5 ns 99 t plal pcs active to ale inactive 12 20 10 18 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15=45 2t clcl C10=40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C2 ns 29 t rhav rd inactive to ad address active (a) t clcl C10=20 t clcl C5=20 ns 41 t dshlh ds inactive to ale active t clch C2=11.5 t clch C2=9.25 59 t rhdx rd high to data hold on ad bus (c) 00ns 66 t avrl a address valid to rd low (a) t clcl + t chcl C3 t clcl + t chcl C1.25 ns 67 t chcsv clkouta high to lcs /ucs valid 0 15 0 10 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns
66 am186ed/edlv microcontrollers preliminary d ra f t read cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 lcs , ucs rd mcs 1Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 a19Ca0 den , ds dt/r s6 s6 bhe (a) ale 1 2 3 4 5 6 8 9 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 29 68 66 67 28 10 uzi ad15Cad8 (b) notes: a am186ed/edlv microcontrollers in 16-bit mode b am186ed/edlv microcontrollers in 8-bit mode c changes in t phase preceding next bus cycle if followed by read, inta, or halt. 59 invalid 23 ad15Cad0 (a) , ad7Cad0 (b) data address s6 status address address bhe (c) (c) 41 99
am186ed/edlv microcontrollers 67 preliminary d ra f t switching characteristics over commercial and industrial operating ranges write cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih = 2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 5t clav ad address valid delay and bhe 0 25 0 20 ns 6t clax address hold 0 25 0 20 ns 7t cldv data valid delay 0 15 0 15 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 25 0 20 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 25 0 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015015ns 21 t cvdex ds inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns 99 t plal pcs active to ale inactive 15 28 15 24 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 025020ns 32 t wlwh wr pulse width 2t clcl C10=90 2t clcl C10=70 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=40 t clcl C10=30 ns 35 t whdex wr inactive to den inactive (a) t clch C3 t clch C3 ns 41 t dshlh ds inactive to ale active t clch C2=21 t clch C2=16 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 67 t chcsv clkouta high to lcs /ucs valid 0 25 0 20 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns 87 t avbl a address valid to whb , wlb low t chcl C3 25 t chcl C3 20 ns 98 t dshdiw ds high to data invalidwrite 35 30 ns
68 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial operating ranges write cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 5t clav ad address valid delay and bhe 0 15 0 12 ns 6t clax address hold 0 0 ns 7t cldv data valid delay 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 15 0 12 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 15 0 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015012ns 21 t cvdex ds inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns 99 t plal pcs active to ale inactive 12 20 10 18 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 015012ns 32 t wlwh wr pulse width 2t clcl C10=50 2t clcl C10=40 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=20 t clcl C10=15 ns 35 t whdex wr inactive to den inactive (a) t clch C3 t clch C3 ns 41 t dshlh ds inactive to ale active t clch C2=11.5 t clch C2=9.25 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C1.25 ns 67 t chcsv clkouta high to lcs /ucs valid 0 15 0 10 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns 87 t avbl a address valid to whb , wlb low t chcl C3 15 t chcl C1.25 12 ns 98 t dshdiw ds high to data invalidwrite 20 15 ns
am186ed/edlv microcontrollers 69 preliminary d ra f t write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 lcs , ucs address data ad15Cad0 (a) , ad7Cad0 (b) wr mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 a19Ca0 den dt/r s6 s6 ale whb , wlb bhe 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 67 68 65 35 31 20 30 34 32 31 33 uzi s6 20 31 87 ad15Cad8 (b) notes: a am186ed/edlv microcontrollers in 16-bit mode b am186ed/edlv microcontrollers in 8-bit mode c changes in t phase preceding next bus cycle if followed by read, inta, or halt invalid 23 ds 21 20 address address 6 bhe 41 20 98 22 22 (c) (c) 99 status
70 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial and industrial operating ranges dram as guaranteed by design, the following table shows the minimum time for ras assertion to ras assertion. these minimums correlate to dram spec t rc . parameter preliminary unit 20 mhz 25 mhz 33 mhz 40 mhz no. symbol description min max min max min max min max general timing responses 101 t chcav clkouta low to column address valid 025020015012ns 102 t clra clkouta low to ras active 325320315312ns 103 t chrx clkouta high to ras inactive 325320315312ns 104 t chca clkouta high to cas active 325320315312ns 105 t clcx clkouta low to cas inactive 325320315312ns 106 t chra clkouta high to ras active 325320315312ns 107 t clrx clkouta low to ras inactive 325320315312ns 108 t rp0w ras inactive pulse width with 0 wait states 60 50 40 30 ns 109 t rp1w ras inactive pulse width with 1 or more wait states 70 60 50 40 ns 110 t rd0w ras to column address delay time with 0 wait states 25 20 15 15 ns 111 t rd1w ras to column address delay time with 1 or more wait states 30 25 20 15 ns wait states 0123 40 mhz 90 110 130 150 33 mhz 110 130 150 170 25 mhz 130 150 170 190 20 mhz 150 170 190 210 frequency
am186ed/edlv microcontrollers 71 preliminary d ra f t dram read cycle timing with no-wait states dram read cycle timing with wait state(s) t 4 t 1 t 2 t 3 t 4 row addr. clkouta ad[15:0] a[17:1] ras cas rd (a) t 3 t 1 note: athe rd output connects to the dram output enable (oe ) pin for read operations. column data 104 1 110 102 103 2 15 5 101 68 108 105 27 25 t 4 t 1 t 2 t 3 t w t 4 row addr. clkouta ad[15:0] a[17:1] ras cas rd (a) t 1 column note: athe rd output connects to the dram output enable (oe ) pin for read operations. data 1 2 107 109 105 27 25 104 102 110 101 68 15 5
72 am186ed/edlv microcontrollers preliminary d ra f t dram write cycle timing with no-wait states dram write cycle timing with wait state(s) t 4 t 1 t 2 t 3 t 4 t 1 data row addr. clkouta ad[15:0] ras cas wr (a) a[17:1] column note: a write operations use the wr output connected to the dram write enable (we ) pin. 5 7 30 103 108 105 31 104 20 102 110 68 101 t 4 t 1 t 2 t 3 t w t 4 t 1 data row addr. clkouta ad[15:0] a[17:1] cas wr (a) ras column note: a write operations use the wr output connected to the dram write enable (we ) pin. 5 7 68 101 102 110 107 104 105 109 31 20 30
am186ed/edlv microcontrollers 73 preliminary d ra f t dram cas -before-ras cycle timing t 4 t 1 t 2 t w t w t w t 3 t 4 x x clkouta ad[15:0] a[17:1] ras cas (a) rd (b) t 1 notes: acas before ras cycle timing is always 7 clocks, independent of wait state timing. bthe rd output connects to the dram output enable (oe ) pin for read operations. ffff 5 15 68 101 106 107 109 105 27 25 104
74 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial and industrial operating ranges interrupt acknowledge cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt/r signals. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 10 10 ns 2t cldx data in hold 3 3 ns general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 7t cldv data valid delay 0 25 0 20 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address invalid to ale low (a) t clch C2 t clch C2 ns 15 t claz ad address float delay t clax =0 25 t clax =0 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 0 25 0 20 ns 21 t cvdex den inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 (c) 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns 31 t cvctx control inactive delay (b) 0 25 0 20 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns
am186ed/edlv microcontrollers 75 preliminary d ra f t switching characteristics over commercial operating ranges interrupt acknowledge cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt/r signals. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 8 5 ns 2t cldx data in hold 3 2 ns general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 7t cldv data valid delay 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 15 t clax =0 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 0 15 0 12 ns 21 t cvdex den inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 (c) 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns 31 t cvctx control inactive delay (b) 0 15 0 12 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns
76 am186ed/edlv microcontrollers preliminary d ra f t interrupt acknowledge cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status ale ad15Cad0 inta 1Cinta 0 den dt/r ptr a19Ca0 s6 bhe bhe 8 1 2 3 4 7 9 10 11 12 15 19 20 22 22 22 68 31 (a) (b) (c) (d) s6 21 notes: a the status bits become inactive in the state preceding t 4 . b the data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to t cldx (min). c this parameter applies for an interrupt acknowledge cycle that follows a write cycle. d if followed by a write cycle, this change occurs in the state preceding that write cycle. 4 invalid 23 address s6
am186ed/edlv microcontrollers 77 preliminary d ra f t switching characteristics over commercial and industrial operating ranges software halt cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den signal. switching characteristics over commercial operating ranges software halt cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den signal. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 5t clav ad address invalid delay and bhe 0 25 0 20 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 22 t chctv control active delay 2 (b) 025020ns 68 t chav clkouta high to a address invalid 0 25 0 20 ns parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 5t clav ad address invalid delay and bhe 0 15 0 12 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 22 t chctv control active delay 2 (b) 015012ns 68 t chav clkouta high to a address invalid 0 15 0 10 ns
78 am186ed/edlv microcontrollers preliminary d ra f t software halt cycle waveforms clkouta t 1 t 2 t i t i s 2Cs 0 status ale invalid address s6, ad15Cad0 den dt/r invalid address a19Ca0 3 4 5 9 10 11 19 22 68
am186ed/edlv microcontrollers 79 preliminary d ra f t switching characteristics over commercial and industrial operating ranges clock (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a the specifications for clkin are applicable to the normal pll and clkdiv2 modes. the pll should be used for operations from 16.667 mhz to 40 mhz. for operations below 16.667 mhz, the clkdiv2 mode should be used. because the clkdiv2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for clkdiv2 mode. for example, use the 20 mhz clkin specifications for 10 mhz operation. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max clkin requirements 36 t ckin x1 period (a) 50 60 40 60 ns 37 t clck x1 low time (1.5 v) (a) 15 15 ns 38 t chck x1 high time (1.5 v) (a) 15 15 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 55ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 55ns clkout timing 42 t clcl clkouta period 50 40 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C2=23 0.5t clcl C2=18 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C2=23 0.5t clcl C2=18 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 33ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 33ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 15 15 ns 70 t cicob x1 to clkoutb skew 25 25 ns
80 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial operating ranges clock (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a the specifications for clkin are applicable to the normal pll and clkdiv2 modes. the pll should be used for operations from 16.667 mhz to 40 mhz. for operations below 16.667 mhz, the clkdiv2 mode should be used. because the clkdiv2 input frequency is two times the system frequency, the specifications for twice the frequency should used for clkdiv2 mode. for example, use the 20 mhz clkin specifications for 10 mhz operation. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max clkin requirements 36 t ckin x1 period (a) 30 60 25 60 ns 37 t clck x1 low time (1.5 v) (a) 10 7.5 ns 38 t chck x1 high time (1.5 v) (a) 10 7.5 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 55ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 55ns clkout timing 42 t clcl clkouta period 30 25 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C1.5 =13.5 0.5t clcl C1.25 =11.25 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C1.5 =13.5 0.5t clcl C1.25 =11.25 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 3 3 ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 3 3 ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 15 15 ns 70 t cicob x1 to clkoutb skew 25 25 ns
am186ed/edlv microcontrollers 81 preliminary d ra f t clock waveforms clock waveformsactive mode clock waveformspower-save mode x1 x2 clkoutb clkouta (active, f=000) 36 37 39 40 42 43 46 69 70 38 44 45 x1 clkouta (power-save, f=010) x2 clkoutb (like clkouta, cbf=0) clkoutb (like x1, cbf=1)
82 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial and industrial operating ranges ready and peripheral (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. switching characteristics over commercial operating ranges ready and peripheral (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. parameter preliminary preliminary unit 20 mhz 25 mhz no. symbol description min max min max ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 10 10 ns 48 t clsry srdy transition hold time (a) 33ns 49 t arych ardy resolution transition setup time (b) 10 10 ns 50 t clarx ardy active hold time (a) 44ns 51 t arychl ardy inactive holding time 6 6 ns 52 t arylcl ardy setup time (a) 15 15 ns 53 t invch peripheral setup time (b) 10 10 ns 54 t invcl drq setup time (b) 10 10 ns peripheral timing responses 55 t cltmv timer output delay 25 20 ns parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 85ns 48 t clsry srdy transition hold time (a) 32ns 49 t arych ardy resolution transition setup time (b) 85ns 50 t clarx ardy active hold time (a) 43ns 51 t arychl ardy inactive holding time 6 5 ns 52 t arylcl ardy setup time (a) 10 5 ns 53 t invch peripheral setup time (b) 85ns 54 t invcl drq setup time (b) 85ns peripheral timing responses 55 t cltmv timer output delay 15 12 ns
am186ed/edlv microcontrollers 83 preliminary d ra f t synchronous, asynchronous, and peripheral waveforms synchronous ready waveforms asynchronous ready waveforms peripheral waveforms clkouta t w t w t w t 4 srdy t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 case 3 case 4 47 48 case 1 clkouta t w t w t w t 4 ardy (normally not- ready system) t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 case 3 case 4 ardy (normally ready system) 49 50 49 51 50 52 case 1 clkouta tmrout1C tmrout0 drq1Cdrq0 int4Cint0, nmi, tmrin1Ctmrin0 53 54 55 54
84 am186ed/edlv microcontrollers preliminary d ra f t switching characteristics over commercial and industrial operating ranges reset and bus hold (20 mhz and 25 mhz) switching characteristics over commercial operating ranges reset and bus hold (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a this timing must be met to guarantee recognition at the next clock. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max reset and bus hold timing requirements 5t clav ad address valid delay and bhe 0 25 0 20 ns 15 t claz ad address float delay 0 25 0 20 ns 57 t resin res setup time 10 10 ns 58 t hvcl hold setup (a) 10 10 ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 25 0 20 ns 63 t chcz command lines float delay 25 20 ns 64 t chcv command lines valid delay (after float) 25 20 ns parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max reset and bus hold timing requirements 5t clav ad address valid delay and bhe 0 15 0 12 ns 15 t claz ad address float delay 0 15 0 12 ns 57 t resin res setup time 8 5 ns 58 t hvcl hold setup (a) 85ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 15 0 12 ns 63 t chcz command lines float delay 15 12 ns 64 t chcv command lines valid delay (after float) 15 12 ns
am186ed/edlv microcontrollers 85 preliminary d ra f t reset and bus hold waveforms reset waveforms signals related to reset waveforms x1 res clkouta 57 57 res s 2/btsel, clkouta bhe /aden , s6/clkdiv 2, and uzi ad15Cad0 three-state three-state
86 am186ed/edlv microcontrollers preliminary d ra f t bus hold waveformsentering bus hold waveformsleaving clkouta t i t i t i ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t 4 t i t i case 2 58 62 15 63 case 1 clkouta t i t i t 1 ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t i t 4 t 1 case 2 t i t i 58 62 64 5 case 1
am186ed/edlv microcontrollers 87 preliminary d ra f t tqfp physical dimensions pql 100, trimmed and formed thin quad flat pack 1.00 ref. 1.60 max 11 ?13 11 ?13 0.50 bsc 100 1 1.35 1.45 15.80 16.20 13.80 14.20 15.80 16.20 13.80 14.20 0.17 0.27 16-038-pqt-2_ai pql100 9.3.96 lv notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only.
88 am186ed/edlv microcontrollers preliminary d ra f t pqfp physical dimensions pqr 100, trimmed and formed plastic quad flat pack notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only. pin 100 pin 50 pin 30 pin 1 i.d. 17.00 17.40 12.35 ref 13.90 14.10 18.85 ref 19.90 20.10 23.00 23.40 0.25 min 2.70 2.90 0.65 basic 3.35 max seating plane 16-038-pqr-1_ah pqr100 dp92 6-20-96 lv pin 80 trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386 and am486 are registered trademarks of advanced micro devices, inc. am186, am188, e86, k86, lan, and amd facts-on-demand are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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